soc/intel/braswell: Clean up devicetree settings

Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.

Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 5 insertions, 5 deletions

diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index a82a4abc28..37ee93cd24 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -113,14 +113,14 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd
 	config = config_of(dev);
 	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
 
-	upd->PcdMrcInitTsegSize   = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0;
-	upd->PcdMrcInitMmioSize   = config->PcdMrcInitMmioSize;
+	upd->PcdMrcInitTsegSize   = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0;
+	upd->PcdMrcInitMmioSize   = 0x800;
 	upd->PcdMrcInitSpdAddr1   = config->PcdMrcInitSpdAddr1;
 	upd->PcdMrcInitSpdAddr2   = config->PcdMrcInitSpdAddr2;
 	upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
-	upd->PcdApertureSize      = config->PcdApertureSize;
-	upd->PcdGttSize           = config->PcdGttSize;
-	upd->PcdLegacySegDecode   = config->PcdLegacySegDecode;
+	upd->PcdApertureSize      = 2;
+	upd->PcdGttSize           = 1;
+	upd->PcdLegacySegDecode   = 0;
 	upd->PcdDvfsEnable        = config->PcdDvfsEnable;
 	upd->PcdCaMirrorEn        = config->PcdCaMirrorEn;
 }