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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-10-25 09:29:10 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:06:49 +0000 |
| commit | fe701ee3982f8c921390aacc45d50871dc86d119 (patch) | |
| tree | 228bd8598a5b34c064bf5420551232e941882606 /src/soc/intel/braswell/romstage/romstage.c | |
| parent | f41cb17fe29923fca898b39d343ccc71c193bea7 (diff) | |
soc/intel/cannonlake: Enable ISH from device
PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.
BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.
Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/romstage/romstage.c')
0 files changed, 0 insertions, 0 deletions