diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-05 15:07:29 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-05-23 01:40:57 +0200 |
| commit | 77ff0b1a01d3d640be55d301b2fcf09a3f840ffe (patch) | |
| tree | c745968f84ca4638f3a27881a5ee3943cf39773f /src/soc/intel/braswell/romstage/Makefile.inc | |
| parent | b5ad827ee584a960212ae983e30cd1a0b18c55a5 (diff) | |
Braswell: Use Baytrail as Comparison Base
Add baytrail source for comparison with Braswell.
BRANCH=none
BUG=None
TEST=None
Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/romstage/Makefile.inc')
| -rw-r--r-- | src/soc/intel/braswell/romstage/Makefile.inc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc new file mode 100644 index 0000000000..345037d51f --- /dev/null +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -0,0 +1,7 @@ +cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +romstage-y += romstage.c +romstage-y += raminit.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c +romstage-y += gfx.c +romstage-y += pmc.c +romstage-y += early_spi.c
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