Braswell: Use Baytrail as Comparison Base

Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 47 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/reset.c b/src/soc/intel/braswell/reset.c
new file mode 100644
index 0000000000..c4cb2abfb7
--- /dev/null
+++ b/src/soc/intel/braswell/reset.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/pmc.h>
+#include <soc/reset.h>
+
+void cold_reset(void)
+{
+	/* S0->S5->S0 trip. */
+	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+}
+
+void warm_reset(void)
+{
+	/* PMC_PLTRST# asserted. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void soft_reset(void)
+{
+	/* Sends INIT# to CPU */
+	outb(RST_CPU, RST_CNT);
+}
+
+void hard_reset(void)
+{
+	/* Don't power cycle on hard_reset(). It's not really clear what the
+	 * semantics should be for the meaning of hard_reset(). */
+	warm_reset();
+}