diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2015-08-23 17:24:43 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:38:57 +0100 |
| commit | b0eb594b34f17ccb357c768f38d0716679e93e7f (patch) | |
| tree | 20c6ce5a301ad186e05ff1d204315576decc09ce /src/soc/intel/braswell/ramstage.c | |
| parent | 103f00daaba07c0bf6688642cbe658873dc5a0a8 (diff) | |
soc/braswell: Set max frequency to be turbo frequency
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using
ratio from MSR_IACORE_TURBO_RATIOS
Also, punit_init needs to be called before enabling this frequency.
Original-Reviewed-on: https://chromium-review.googlesource.com/295268
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/ramstage.c')
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1e085d7e93..155c8a2e46 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Perform silicon specific init. */ intel_silicon_init(); + set_max_freq(); set_board_id(); /* Get GPIO initial states from mainboard */ |