diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2015-08-05 17:01:55 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-14 19:17:01 +0100 |
| commit | 45a221de7923d6c1d52f9ca14a3419e7d0803636 (patch) | |
| tree | e3f742125a2939b6a035720ccb2b5820934b375c /src/soc/intel/braswell/ramstage.c | |
| parent | baf00e6b28efcf02497a566fa6f0f43d11304406 (diff) | |
soc/braswell: Fix P-state table
Incorrect bus-core-ratio been used to generate P-state table
Original-Reviewed-on: https://chromium-review.googlesource.com/290681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/ramstage.c')
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 749feaff52..1e085d7e93 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -128,7 +128,7 @@ static void fill_in_pattrs(void) attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ /* Set bus clock speed */ - attrs->bclk_khz = BUS_FREQ_KHZ; + attrs->bclk_khz = cpu_bus_freq_khz(); } static inline void set_acpi_sleep_type(int val) |