diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-08 16:16:34 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-17 14:23:52 +0000 |
| commit | e73da80d2c63f14cdc301a2436cf9b93dc5a531f (patch) | |
| tree | efe173ba2c2485a11ea04af0a4c4e94df8292bfb /src/soc/intel/braswell/ramstage.c | |
| parent | a1c8b34d7b1b3a8df5b86faab79010c06b037445 (diff) | |
braswell: Switch to using common ACPI _SWS code
Switch braswell to use the common code for filling out the NVS
data used by ACPI _SWS methods. This code was out of date on
braswell so also update it to provide the \_GPE.SWS method.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-cyan coreboot
Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/ramstage.c')
| -rw-r--r-- | src/soc/intel/braswell/ramstage.c | 29 |
1 files changed, 8 insertions, 21 deletions
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 26c23bc486..2454c6b141 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -39,6 +39,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/ramstage.h> +#include <soc/intel/common/acpi.h> #include <soc/intel/common/ramstage.h> #include <boardid.h> #include <stdlib.h> @@ -142,30 +143,18 @@ static inline void set_acpi_sleep_type(int val) #endif } -/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ -static void s3_save_acpi_wake_source(global_nvs_t *gnvs) +/* Save wake source information for calculating ACPI _SWS values */ +int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - uint16_t pm1; + static uint32_t gpe0_sts; - if (!ps) - return; - - pm1 = ps->pm1_sts & ps->pm1_en; - - /* Scan for first set bit in PM1 */ - for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { - if (pm1 & 1) - break; - pm1 >>= 1; - } + *pm1 = ps->pm1_sts & ps->pm1_en; - /* If unable to determine then return -1 */ - if (gnvs->pm1i >= 16) - gnvs->pm1i = -1; + gpe0_sts = ps->gpe0_sts & ps->gpe0_en; + *gpe0 = &gpe0_sts; - printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", - gnvs->pm1i); + return 1; } static void s3_resume_prepare(void) @@ -184,8 +173,6 @@ static void s3_resume_prepare(void) } set_acpi_sleep_type(3); - - s3_save_acpi_wake_source(gnvs); } static void set_board_id(void) |