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authorJeremy Soller <jeremy@system76.com>2020-12-29 11:17:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2021-01-21 11:01:08 +0000
commit98d580b8fbd2cf9ccafc2dd0ad48ae7d5ba86186 (patch)
tree3e0c7aa140eb8c13c934ab0bc371f2674e95a307 /src/soc/intel/braswell/pmutil.c
parent3b6b9c7b783f2005952c1521dba30fd5b598e68e (diff)
soc/intel/cannonlake: Allow RP#1 usage for ClkSrc
0 is converted to not used, so use a special value to allow using PCIe root port #1. Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/intel/braswell/pmutil.c')
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