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| author | Rob Barnes <robbarnes@google.com> | 2020-03-05 13:09:32 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-05-21 22:30:27 +0000 |
| commit | 30ce0f383f2f3cf47e3f8cef2ea4ce2f7b478be9 (patch) | |
| tree | 6a286cea4aecf0eeba770adf6ac5f281e61c4735 /src/soc/intel/braswell/pcie.c | |
| parent | 6de79b9a1dedfb36e30a932f300de4ad8a5d27b4 (diff) | |
util/amdfwtool: Fix MAX_PSP_ENTRIES value
Had to increase MAX_PSP_ENTRIES to accommodate the 16 APCBs we have
the ability to add.
BUG=b:150862063
TEST=Boot Trembyle
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I64eccfa28839768788f53327caf187a564842162
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2090323
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/pcie.c')
0 files changed, 0 insertions, 0 deletions