diff options
| author | Caesar Wang <wxt@rock-chips.com> | 2017-02-27 17:55:39 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-25 10:51:28 +0200 |
| commit | 01cbe3b75ae6325d3f9b0de0d56d72d82286940e (patch) | |
| tree | a8e4bf7e3c0076ed4b49e1d280ffec4829851d1a /src/soc/intel/braswell/pcie.c | |
| parent | 7e438af99575365a97f87f59e83e1224571ac5c2 (diff) | |
google/gru: change the sd power sequence
In the safety considerations, we should make sure the slot of SD is
enabled first, since we want to the power switch of corresponding is
powered up.
The different boards have the different power switch for sdmmc.
Some power switch IC need turn on delay for long time.
let's move the slot power of SD to romstage and avoid explicit delays
or per-board.
BRANCH=none
BUG=b:35813418, b:35573103
TEST=check the signal for children of gru, and boot up from sd card.
Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea1b01cc13628033b85251dbb44407f075efdc85
Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/447076
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19430
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/braswell/pcie.c')
0 files changed, 0 insertions, 0 deletions