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authorLee Leahy <leroy.p.leahy@intel.com>2015-05-05 15:07:29 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-05-23 01:40:57 +0200
commit77ff0b1a01d3d640be55d301b2fcf09a3f840ffe (patch)
treec745968f84ca4638f3a27881a5ee3943cf39773f /src/soc/intel/braswell/microcode
parentb5ad827ee584a960212ae983e30cd1a0b18c55a5 (diff)
Braswell: Use Baytrail as Comparison Base
Add baytrail source for comparison with Braswell. BRANCH=none BUG=None TEST=None Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/microcode')
-rw-r--r--src/soc/intel/braswell/microcode/Makefile.inc1
-rw-r--r--src/soc/intel/braswell/microcode/microcode_blob.c3
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc
new file mode 100644
index 0000000000..09bd454ce0
--- /dev/null
+++ b/src/soc/intel/braswell/microcode/Makefile.inc
@@ -0,0 +1 @@
+cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c
new file mode 100644
index 0000000000..7c7b6f10b6
--- /dev/null
+++ b/src/soc/intel/braswell/microcode/microcode_blob.c
@@ -0,0 +1,3 @@
+unsigned microcode[] = {
+#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h"
+};