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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 10:04:57 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 16:36:28 +0000 |
| commit | ad87d1c8b9285cfed47b3ec060be520a467189ff (patch) | |
| tree | 0adc68a09791bbd29cd3ffc78de51a3a7805ffa6 /src/soc/intel/braswell/lpe.c | |
| parent | 2ec1c13ac4a9724095ce71783fd52f70a0b1536d (diff) | |
soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/lpe.c')
0 files changed, 0 insertions, 0 deletions