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authorKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-19 18:39:22 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2022-11-28 10:08:23 +0000
commite8a3af10691a4831a85d8760f7fcb20f78065f78 (patch)
treedff1c9bbfdee73e0283223c334b168ab4b0c4662 /src/soc/intel/braswell/include
parent560c3f5ccfff0fc289bb46f1b1b6c4236817590a (diff)
sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT
Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
-rw-r--r--src/soc/intel/braswell/include/soc/pm.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index 6cb8d55873..131a996919 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -184,6 +184,8 @@
# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */
#define GPE_CTRL 0x40
#define PM2A_CNT_BLK 0x50
+
+#if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO_RLD 0x60
#define TCO_STS 0x64
# define SECOND_TO_STS (1 << 17)
@@ -192,6 +194,7 @@
# define TCO_LOCK (1 << 12)
# define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70
+#endif
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)