diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-08 16:16:34 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-17 14:23:52 +0000 |
| commit | e73da80d2c63f14cdc301a2436cf9b93dc5a531f (patch) | |
| tree | efe173ba2c2485a11ea04af0a4c4e94df8292bfb /src/soc/intel/braswell/include | |
| parent | a1c8b34d7b1b3a8df5b86faab79010c06b037445 (diff) | |
braswell: Switch to using common ACPI _SWS code
Switch braswell to use the common code for filling out the NVS
data used by ACPI _SWS methods. This code was out of date on
braswell so also update it to provide the \_GPE.SWS method.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-cyan coreboot
Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/nvs.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 9492f2c61b..23bd719570 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -46,8 +46,9 @@ typedef struct { u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ - u8 bdid; /* 0x19 - Board ID */ - u8 rsvd1[6]; + u32 gpei; /* 0x19 - GPE Wake Source */ + u8 bdid; /* 0x1d - Board ID */ + u8 rsvd1[2]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ |