diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:20:26 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:32:09 +0200 |
| commit | 1b6196dec95e12ae44b5cfe62073c3dcd3f52686 (patch) | |
| tree | cee76a83606e8d76939225c01003b2240c4ce3cd /src/soc/intel/braswell/include | |
| parent | f5cfaa39342bed7dbf3abe19486089c4cf8a4561 (diff) | |
soc/intel/braswell: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Ia3860fe9e5229917881696e08418c3fd5fb64ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/pm.h | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index ec10101b5b..3d11330efb 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -17,6 +17,7 @@ #ifndef _SOC_PM_H_ #define _SOC_PM_H_ +#include <arch/acpi.h> #define IOCOM1 0x3f8 @@ -148,14 +149,6 @@ #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) @@ -214,11 +207,6 @@ # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 -/* Generic sleep state types */ -#define SLEEP_STATE_S0 0 -#define SLEEP_STATE_S3 3 -#define SLEEP_STATE_S5 5 - #if !defined(__ASSEMBLER__) && !defined(__ACPI__) /* Track power state from reset to log events. */ |