summaryrefslogtreecommitdiff
path: root/src/soc/intel/braswell/include
diff options
context:
space:
mode:
authorFrans Hendriks <fhendriks@eltan.com>2018-07-13 09:52:04 +0200
committerMartin Roth <martinroth@google.com>2018-09-21 14:14:10 +0000
commit83e73249693f3aabc1d47212ab45c3acd792c9ee (patch)
tree5b9e972fe9e68496be04424ff7ce3b7efba13006 /src/soc/intel/braswell/include
parentdc0352835525598e0c72d6fbcfba428113847e59 (diff)
soc/intel/braswell/ramstage.c: Add SoC stepping D-1 support
No support for SoC D-1 stepping is available. According to Intel doc #332095-015 stepping C-0 has revision id 0x21 and D-1 revision ID 0x35. Also correct the RID_C_STEPPING_START value for C-0. BUG=none TEST=Built, Intel Cherry Hill Rev F. Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27471 Reviewed-by: Wim Vervoorn Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/include')
-rw-r--r--src/soc/intel/braswell/include/soc/lpc.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h
index d842274583..7b1e3424e9 100644
--- a/src/soc/intel/braswell/include/soc/lpc.h
+++ b/src/soc/intel/braswell/include/soc/lpc.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -36,7 +37,8 @@
#define RID_A_STEPPING_START 1
#define RID_B_STEPPING_START 5
-#define RID_C_STEPPING_START 0xe
+#define RID_C_STEPPING_START 0x21
+#define RID_D_STEPPING_START 0x35
enum soc_stepping {
STEP_A0,
STEP_A1,
@@ -45,6 +47,7 @@ enum soc_stepping {
STEP_B2,
STEP_B3,
STEP_C0,
+ STEP_D1,
};
/* Registers behind the RCBA_BASE_ADDRESS bar. */