diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2019-06-18 12:18:55 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-20 15:41:37 +0000 |
| commit | 863853cd2d8e01db2045e73d96c502e4ecba8ad1 (patch) | |
| tree | f3c64fa27ccce037ca5b47a45a41ae7014ba4083 /src/soc/intel/braswell/include | |
| parent | e48be35bca9a0656d1becb0c8a030a11eb8ffaa7 (diff) | |
soc/intel/braswell/smbus.c: Add support for i2c mode block write
Intel Braswell supports i2c block write using SMBus controller.
smbus_i2c_block_write() is added to configure SMBus controller in i2c
mode before calling do_i2c_block_write().
Add smbus.c to ramstage.
BUG=N/A
TEST=Verify LCD display is working on Facebook FBG-1701
Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/smbus.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h new file mode 100644 index 0000000000..8bc62f7eec --- /dev/null +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +/* PCI Configuration Space SMBus */ +#define HOSTC 0x40 +#define HOSTC_I2C_EN (1 << 2) + +int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf); +#endif /* _SOC_SMBUS_H_ */ |