diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 17:46:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-27 10:25:03 +0000 |
| commit | 4abc73183134def757c553aa4eb195fffa824100 (patch) | |
| tree | e6fa253f8e7dc46e80a0a33ea903b4fe0be83419 /src/soc/intel/braswell/include | |
| parent | aeffa86cc551110b62074fa6302f4960d87a9a8c (diff) | |
ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/include')
| -rw-r--r-- | src/soc/intel/braswell/include/soc/device_nvs.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/nvs.h | 10 |
2 files changed, 2 insertions, 12 deletions
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 73af09ad41..bf8974d840 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -24,7 +24,7 @@ #define SCC_NVS_SDIO 1 #define SCC_NVS_SD 2 -typedef struct { +struct __packed device_nvs { /* Device Enabled in ACPI Mode */ u8 lpss_en[14]; u8 scc_en[3]; @@ -42,6 +42,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ -} __packed device_nvs_t; +}; #endif /* _SOC_DEVICE_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 41bb5a1a54..7d27c3f822 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -4,7 +4,6 @@ #define _SOC_NVS_H_ #include <stdint.h> -#include <soc/device_nvs.h> struct __packed global_nvs { /* Miscellaneous */ @@ -45,15 +44,6 @@ struct __packed global_nvs { u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */ - - u8 unused[76]; - - /* ChromeOS specific (0x100-0xfff) */ - u8 chromeos_reserve[0xf00]; - - /* LPSS (0x1000) */ - device_nvs_t dev; }; #endif /* _SOC_NVS_H_ */ |