diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:20:28 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-25 21:50:48 +0200 |
| commit | 32471729d9ebbabe809711ec55568925c6ce2070 (patch) | |
| tree | b9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/emmc.c | |
| parent | 5fe62efb77a2ecfeecdcc526404712b816e74693 (diff) | |
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/emmc.c')
| -rw-r--r-- | src/soc/intel/braswell/emmc.c | 29 |
1 files changed, 9 insertions, 20 deletions
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 3c65de3f76..7420205410 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,46 +33,34 @@ #include "chip.h" static const struct reg_script emmc_ops[] = { - /* Enable 2ms card stable feature. */ - REG_PCI_OR32(0xa8, (1 << 24)), - /* Enable HS200 */ - REG_PCI_WRITE32(0xa0, 0x446cc801), - REG_PCI_WRITE32(0xa4, 0x80000807), - /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ - REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), - /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ - REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), - /* Set slew for HS200 */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), - /* Max timeout */ - REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), REG_SCRIPT_END, }; static void emmc_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); - if (config->scc_acpi_mode) + if (config->emmc_acpi_mode) { + printk(BIOS_DEBUG, "Enabling ACPI mode\n"); scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + } } -static struct device_operations device_ops = { +static struct device_operations emmc_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = emmc_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, + .ops = &emmc_device_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = MMC_DEVID, }; |