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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-30 20:23:09 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-15 03:52:49 +0000 |
| commit | 86091f94b6ca58f4b8795503b274492d6a935c15 (patch) | |
| tree | db6e5f77dc57850b25574aed5063743ca4bc4d48 /src/soc/intel/braswell/cpu.c | |
| parent | 58562405c8c416a415652516b8af31b204b4ff0d (diff) | |
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/braswell/cpu.c')
| -rw-r--r-- | src/soc/intel/braswell/cpu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 2ab8725818..41a43ee50b 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -206,10 +206,10 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRRphysBase_MSR, smrr); + wrmsr(SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRRphysMask_MSR, smrr); + wrmsr(SMRR_PHYS_MASK, smrr); /* * The relocated handler runs with all CPUs concurrently. Therefore @@ -284,7 +284,7 @@ static int smm_load_handlers(void) relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; - relo_attrs.smrr_mask |= MTRRphysMaskValid; + relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { |