diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-27 13:04:28 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-01 16:02:13 +0000 |
| commit | 8d5b6747391919a8de05dd19308acc79f2b22659 (patch) | |
| tree | 5a7149d7c0f8a53de9880daf20d93c5d2f5c7f3a /src/soc/intel/braswell/chip.h | |
| parent | fbca40c9cc127487e73a602bd2332bca866cdbdb (diff) | |
soc/intel/braswell: Set GNVS DPTE via devicetree
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS
field, as newer Intel platforms do.
Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell/chip.h')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index d493ad1688..53627be577 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -42,6 +42,8 @@ enum usb_comp_bg_value { struct soc_intel_braswell_config { bool enable_xdp_tap; + bool dptf_enable; + enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ |