diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-08-28 17:21:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:31:13 +0000 |
| commit | 3745c65c832ab0abb557cf68e92a6ad2c09f0faf (patch) | |
| tree | 4268f2ab09a346f76b1427fd8071f66979437f98 /src/soc/intel/braswell/chip.h | |
| parent | 15c220dc3918755b72ac7eb1e128fc65c6b64cf7 (diff) | |
skylake: Apply USB2 and USB3 port enable/disable settings
The USB port enable/disable settings were never getting applied to
the UPD configuration and so were not getting used by FSP.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados
Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296034
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/chip.h')
0 files changed, 0 insertions, 0 deletions