soc/intel/braswell: Fix most of the issues detected by checkpatch

Fix the following errors and warnings detected by checkpatch.pl:

ERROR: that open brace { should be on the previous line
ERROR: return is not a function, parentheses are not required
WARNING: braces {} are not necessary for any arm of this statement
WARNING: line over 80 characters
WARNING: braces {} are not necessary for single statement blocks
WARNING: Avoid unnecessary line continuations
WARNING: break is not useful after a goto or return
WARNING: else is not generally useful after a break or return

False positives are generated by checkpatch for the following test:
ERROR: Macros with complex values should be enclosed in parentheses

TEST=Build for cyan

Change-Id: I19048895145b138a63100b29f829ff446ff71b58
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18871
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)

1 files changed, 1 insertions, 1 deletions

diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index fc57a6a95d..8c3f143b46 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -58,7 +58,7 @@ struct soc_intel_braswell_config {
 	int disable_slp_x_stretch_sus_fail;
 
 	/* LPE Audio Clock configuration. */
-	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */
+	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */
 
 	/* Native SD Card controller - override controller capabilities. */
 	uint32_t sdcard_cap_low;