soc/intel/braswell: Clean up

Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.

Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 83 insertions, 86 deletions

diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index be95808910..026e491006 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -58,13 +58,13 @@ struct soc_intel_braswell_config {
 
 	enum serirq_mode serirq_mode;
 
-	/* Disable SLP_X stretching after SUS power well loss. */
+	/* Disable SLP_X stretching after SUS power well loss */
 	int disable_slp_x_stretch_sus_fail;
 
-	/* LPE Audio Clock configuration. */
-	enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */
+	/* LPE Audio Clock configuration */
+	enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */
 
-	/* Native SD Card controller - override controller capabilities. */
+	/* Native SD Card controller - override controller capabilities */
 	uint32_t sdcard_cap_low;
 	uint32_t sdcard_cap_high;
 
@@ -74,7 +74,7 @@ struct soc_intel_braswell_config {
 	int sd_acpi_mode;
 	int lpe_acpi_mode;
 
-	/* Allow PCIe devices to wake system from suspend. */
+	/* Allow PCIe devices to wake system from suspend */
 	int pcie_wake_enable;
 
 	/* Program USB2_COMPBG register.
@@ -84,94 +84,91 @@ struct soc_intel_braswell_config {
 	 */
 	enum usb_comp_bg_value usb_comp_bg;
 
-
 	/*
 	 * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
-	 * These are configuration values that are passed to FSP during
-	 * MemoryInit.
+	 * These are configuration values that are passed to FSP during MemoryInit.
 	 */
-	UINT16 PcdMrcInitTsegSize;
-	UINT16 PcdMrcInitMmioSize;
-	UINT8  PcdMrcInitSpdAddr1;
-	UINT8  PcdMrcInitSpdAddr2;
-	UINT8  PcdIgdDvmt50PreAlloc;
-	UINT8  PcdApertureSize;
-	UINT8  PcdGttSize;
-	UINT8  PcdLegacySegDecode;
-	UINT8  PcdDvfsEnable;
-	UINT8  PcdCaMirrorEn; /* Command Address Mirroring Enabled */
+	uint16_t PcdMrcInitTsegSize;
+	uint16_t PcdMrcInitMmioSize;
+	uint8_t  PcdMrcInitSpdAddr1;
+	uint8_t  PcdMrcInitSpdAddr2;
+	uint8_t  PcdIgdDvmt50PreAlloc;
+	uint8_t  PcdApertureSize;
+	uint8_t  PcdGttSize;
+	uint8_t  PcdLegacySegDecode;
+	uint8_t  PcdDvfsEnable;
+	uint8_t  PcdCaMirrorEn; /* Command Address Mirroring Enabled */
 
 	/*
 	 * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
-	 * These are configuration values that are passed to FSP during
-	 * SiliconInit.
+	 * These are configuration values that are passed to FSP during SiliconInit.
 	 */
-	UINT8  PcdSdcardMode;
-	UINT8  PcdEnableHsuart0;
-	UINT8  PcdEnableHsuart1;
-	UINT8  PcdEnableAzalia;
-	UINT8  PcdEnableSata;
-	UINT8  PcdEnableXhci;
-	UINT8  PcdEnableLpe;
-	UINT8  PcdEnableDma0;
-	UINT8  PcdEnableDma1;
-	UINT8  PcdEnableI2C0;
-	UINT8  PcdEnableI2C1;
-	UINT8  PcdEnableI2C2;
-	UINT8  PcdEnableI2C3;
-	UINT8  PcdEnableI2C4;
-	UINT8  PcdEnableI2C5;
-	UINT8  PcdEnableI2C6;
-	UINT8  PunitPwrConfigDisable;
-	UINT8  ChvSvidConfig;
-	UINT8  DptfDisable;
-	UINT8  PcdEmmcMode;
-	UINT8  PcdUsb3ClkSsc;
-	UINT8  PcdDispClkSsc;
-	UINT8  PcdSataClkSsc;
-	UINT8  Usb2Port0PerPortPeTxiSet;
-	UINT8  Usb2Port0PerPortTxiSet;
-	UINT8  Usb2Port0IUsbTxEmphasisEn;
-	UINT8  Usb2Port0PerPortTxPeHalf;
-	UINT8  Usb2Port1PerPortPeTxiSet;
-	UINT8  Usb2Port1PerPortTxiSet;
-	UINT8  Usb2Port1IUsbTxEmphasisEn;
-	UINT8  Usb2Port1PerPortTxPeHalf;
-	UINT8  Usb2Port2PerPortPeTxiSet;
-	UINT8  Usb2Port2PerPortTxiSet;
-	UINT8  Usb2Port2IUsbTxEmphasisEn;
-	UINT8  Usb2Port2PerPortTxPeHalf;
-	UINT8  Usb2Port3PerPortPeTxiSet;
-	UINT8  Usb2Port3PerPortTxiSet;
-	UINT8  Usb2Port3IUsbTxEmphasisEn;
-	UINT8  Usb2Port3PerPortTxPeHalf;
-	UINT8  Usb2Port4PerPortPeTxiSet;
-	UINT8  Usb2Port4PerPortTxiSet;
-	UINT8  Usb2Port4IUsbTxEmphasisEn;
-	UINT8  Usb2Port4PerPortTxPeHalf;
-	UINT8  Usb3Lane0Ow2tapgen2deemph3p5;
-	UINT8  Usb3Lane1Ow2tapgen2deemph3p5;
-	UINT8  Usb3Lane2Ow2tapgen2deemph3p5;
-	UINT8  Usb3Lane3Ow2tapgen2deemph3p5;
-	UINT8  PcdSataInterfaceSpeed;
-	UINT8  PcdPchUsbSsicPort;
-	UINT8  PcdPchUsbHsicPort;
-	UINT8  PcdPcieRootPortSpeed;
-	UINT8  PcdPchSsicEnable;
-	UINT32 PcdLogoPtr;
-	UINT32 PcdLogoSize;
-	UINT8  PcdRtcLock;
-	UINT8  PMIC_I2CBus;
-	UINT8  ISPEnable;
-	UINT8  ISPPciDevConfig;
-	UINT8  PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/
-	UINT8  I2C0Frequency;  /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */
-	UINT8  I2C1Frequency;
-	UINT8  I2C2Frequency;
-	UINT8  I2C3Frequency;
-	UINT8  I2C4Frequency;
-	UINT8  I2C5Frequency;
-	UINT8  I2C6Frequency;
+	uint8_t  PcdSdcardMode;
+	uint8_t  PcdEnableHsuart0;
+	uint8_t  PcdEnableHsuart1;
+	uint8_t  PcdEnableAzalia;
+	uint8_t  PcdEnableSata;
+	uint8_t  PcdEnableXhci;
+	uint8_t  PcdEnableLpe;
+	uint8_t  PcdEnableDma0;
+	uint8_t  PcdEnableDma1;
+	uint8_t  PcdEnableI2C0;
+	uint8_t  PcdEnableI2C1;
+	uint8_t  PcdEnableI2C2;
+	uint8_t  PcdEnableI2C3;
+	uint8_t  PcdEnableI2C4;
+	uint8_t  PcdEnableI2C5;
+	uint8_t  PcdEnableI2C6;
+	uint8_t  PunitPwrConfigDisable;
+	uint8_t  ChvSvidConfig;
+	uint8_t  DptfDisable;
+	uint8_t  PcdEmmcMode;
+	uint8_t  PcdUsb3ClkSsc;
+	uint8_t  PcdDispClkSsc;
+	uint8_t  PcdSataClkSsc;
+	uint8_t  Usb2Port0PerPortPeTxiSet;
+	uint8_t  Usb2Port0PerPortTxiSet;
+	uint8_t  Usb2Port0IUsbTxEmphasisEn;
+	uint8_t  Usb2Port0PerPortTxPeHalf;
+	uint8_t  Usb2Port1PerPortPeTxiSet;
+	uint8_t  Usb2Port1PerPortTxiSet;
+	uint8_t  Usb2Port1IUsbTxEmphasisEn;
+	uint8_t  Usb2Port1PerPortTxPeHalf;
+	uint8_t  Usb2Port2PerPortPeTxiSet;
+	uint8_t  Usb2Port2PerPortTxiSet;
+	uint8_t  Usb2Port2IUsbTxEmphasisEn;
+	uint8_t  Usb2Port2PerPortTxPeHalf;
+	uint8_t  Usb2Port3PerPortPeTxiSet;
+	uint8_t  Usb2Port3PerPortTxiSet;
+	uint8_t  Usb2Port3IUsbTxEmphasisEn;
+	uint8_t  Usb2Port3PerPortTxPeHalf;
+	uint8_t  Usb2Port4PerPortPeTxiSet;
+	uint8_t  Usb2Port4PerPortTxiSet;
+	uint8_t  Usb2Port4IUsbTxEmphasisEn;
+	uint8_t  Usb2Port4PerPortTxPeHalf;
+	uint8_t  Usb3Lane0Ow2tapgen2deemph3p5;
+	uint8_t  Usb3Lane1Ow2tapgen2deemph3p5;
+	uint8_t  Usb3Lane2Ow2tapgen2deemph3p5;
+	uint8_t  Usb3Lane3Ow2tapgen2deemph3p5;
+	uint8_t  PcdSataInterfaceSpeed;
+	uint8_t  PcdPchUsbSsicPort;
+	uint8_t  PcdPchUsbHsicPort;
+	uint8_t  PcdPcieRootPortSpeed;
+	uint8_t  PcdPchSsicEnable;
+	uint32_t PcdLogoPtr;
+	uint32_t PcdLogoSize;
+	uint8_t  PcdRtcLock;
+	uint8_t  PMIC_I2CBus;
+	uint8_t  ISPEnable;
+	uint8_t  ISPPciDevConfig;
+	uint8_t  PcdSdDetectChk; /* Enable / Disable SD Card Detect Simulation */
+	uint8_t  I2C0Frequency;  /* 0 - 100KHz, 1 - 400KHz, 2 - 1MHz */
+	uint8_t  I2C1Frequency;
+	uint8_t  I2C2Frequency;
+	uint8_t  I2C3Frequency;
+	uint8_t  I2C4Frequency;
+	uint8_t  I2C5Frequency;
+	uint8_t  I2C6Frequency;
 };
 
 #endif /* _SOC_CHIP_H_ */