diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2015-08-07 18:22:54 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:55:27 +0000 |
| commit | 13cd3310a55c5683fb0b1176444ad8f5e5243945 (patch) | |
| tree | f2a2f4e423bd0e880d5d43efd3cf077d605ffb91 /src/soc/intel/braswell/chip.h | |
| parent | 951f2d3ebb391bf4b08cb0073c96689fa453a94d (diff) | |
Braswell: Modify CB to accomodate new FSPv83
Latest FSPv83 made some change related to UPD/VPD
need this patch to align those
BUG=None
TEST=Build and Boot Cyan System
BRANCH=strago-7287.B
CQ-DEPEND=CL:*226897
Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291394
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303137
Original-Commit-Ready: John Zhao <john.zhao@intel.com>
Original-Tested-by: John Zhao <john.zhao@intel.com>
Change-Id: I9920eea84b802699454850bfde489668201ffeb6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/chip.h')
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index ff68014d9c..e415dfd78b 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -85,7 +85,6 @@ struct soc_intel_braswell_config { UINT8 PcdEnableHsuart0; UINT8 PcdEnableHsuart1; UINT8 PcdEnableAzalia; - UINT32 AzaliaConfigPtr; UINT8 PcdEnableSata; UINT8 PcdEnableXhci; UINT8 PcdEnableLpe; @@ -98,7 +97,6 @@ struct soc_intel_braswell_config { UINT8 PcdEnableI2C4; UINT8 PcdEnableI2C5; UINT8 PcdEnableI2C6; - UINT32 PcdGraphicsConfigPtr; UINT8 PunitPwrConfigDisable; UINT8 ChvSvidConfig; UINT8 DptfDisable; |