diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 17:20:16 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-14 11:05:51 +0000 |
| commit | 233ae1919b72434ca6cd783c9a946d32953bc7e9 (patch) | |
| tree | 52034859f35a1ab58e6f870b2b040e33d8eeda5d /src/soc/intel/braswell/chip.c | |
| parent | 68cf57cf33141edcc8b4b1250b099884e0553457 (diff) | |
soc/intel/braswell: Clean up devicetree settings
Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/braswell/chip.c')
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 25965a04a7..2adda5494f 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -81,9 +81,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->ChvSvidConfig = config->ChvSvidConfig; params->DptfDisable = config->DptfDisable; params->PcdEmmcMode = config->PcdEmmcMode; - params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; - params->PcdDispClkSsc = config->PcdDispClkSsc; - params->PcdSataClkSsc = config->PcdSataClkSsc; + params->PcdUsb3ClkSsc = 1; + params->PcdDispClkSsc = 1; + params->PcdSataClkSsc = 1; params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; @@ -115,14 +115,14 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5; - params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; + params->PcdSataInterfaceSpeed = 3; params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; - params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; + params->PcdPcieRootPortSpeed = 0; params->PcdPchSsicEnable = config->PcdPchSsicEnable; params->PcdLogoPtr = config->PcdLogoPtr; params->PcdLogoSize = config->PcdLogoSize; - params->PcdRtcLock = config->PcdRtcLock; + params->PcdRtcLock = 0; params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; |