Braswell: Use Baytrail as Comparison Base

Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 98 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc
new file mode 100644
index 0000000000..3a4025198c
--- /dev/null
+++ b/src/soc/intel/braswell/bootblock/Makefile.inc
@@ -0,0 +1 @@
+chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
new file mode 100644
index 0000000000..9d7f19c4c7
--- /dev/null
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <soc/iosf.h>
+#include <cpu/intel/microcode/microcode.c>
+
+static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
+{
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	/* Why only top 4MiB ? */
+	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void setup_mmconfig(void)
+{
+	uint32_t reg;
+
+	/* Set up the MMCONF range. The register lives in the BUNIT. The
+	 * IO variant of the config access needs to be used initially to
+	 * properly configure as the IOSF access registers live in PCI
+	 * config space. */
+	reg = 0;
+	/* Clear the extended register. */
+	pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
+	reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
+	pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
+	reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
+	      IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
+	pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
+}
+
+static void bootblock_cpu_init(void)
+{
+	/* Allow memory-mapped PCI config access. */
+	setup_mmconfig();
+
+	/* Load microcode before any caching. */
+	intel_update_microcode_from_cbfs();
+	enable_rom_caching();
+}
diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc
new file mode 100644
index 0000000000..3db5c35c4d
--- /dev/null
+++ b/src/soc/intel/braswell/bootblock/timestamp.inc
@@ -0,0 +1,18 @@
+/* Store the initial timestamp for booting in mmx registers. This works
+ * because the bootblock isn't being compiled with MMX support so mm0 and
+ * mm1 will be preserved into romstage. */
+	.code32
+
+.global stash_timestamp
+stash_timestamp:
+
+	/* Save the BIST value */
+	movl	%eax, %ebp
+
+	finit
+	rdtsc
+	movd	%eax, %mm0
+	movd	%edx, %mm1
+
+	/* Restore the BIST value to %eax */
+	movl	%ebp, %eax