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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-19 14:12:19 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-28 08:58:13 +0000 |
| commit | fa5f9b5aff2279d6304a8b197e12714934025575 (patch) | |
| tree | b98a0171164a119eca68ebf699e545c5c32d9f9c /src/soc/intel/braswell/acpi | |
| parent | e76ce871c8f84aef38fbf9df9c8bee3c10c085d7 (diff) | |
ACPI: Declare GNVS variables globally
There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.
Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi')
| -rw-r--r-- | src/soc/intel/braswell/acpi/device_nvs.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/acpi/globalnvs.asl | 10 |
2 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index aa0e9533f8..d570788985 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -External (NVSD) - -OperationRegion (DNVS, SystemMemory, NVSD, 0x1000) Field (DNVS, ByteAcc, NoLock, Preserve) { /* Device Enabled in ACPI Mode */ diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 6aa595713b..628a79190a 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -4,16 +4,6 @@ Name(\PICM, 0) /* IOAPIC/8259 */ -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ |