Braswell: Use Baytrail as Comparison Base

Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

20 files changed, 3151 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl
new file mode 100644
index 0000000000..f7e404daba
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/cpu.asl
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CP00, DeviceObj)
+External (\_PR.CP01, DeviceObj)
+External (\_PR.CP02, DeviceObj)
+External (\_PR.CP03, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x81)  // _CST
+		Notify (\_PR.CP01, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x81)  // _CST
+		Notify (\_PR.CP03, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x80)  // _PPC
+		Notify (\_PR.CP01, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x80)  // _PPC
+		Notify (\_PR.CP03, 0x80)  // _PPC
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CP00, 0x82)  // _TPC
+		Notify (\_PR.CP01, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CP02, 0x82)  // _TPC
+		Notify (\_PR.CP03, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 4)) {
+		Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package() {\_PR.CP00, \_PR.CP01})
+	} Else {
+		Return (Package() {\_PR.CP00})
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl
new file mode 100644
index 0000000000..fce7b53054
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/device_nvs.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Device Enabled in ACPI Mode */
+
+S0EN,	8,	// SDMA Enable
+S1EN,	8,	// I2C1 Enable
+S2EN,	8,	// I2C2 Enable
+S3EN,	8,	// I2C3 Enable
+S4EN,	8,	// I2C4 Enable
+S5EN,	8,	// I2C5 Enable
+S6EN,	8,	// I2C6 Enable
+S7EN,	8,	// I2C7 Enable
+S8EN,	8,	// SDMA2 Enable
+S9EN,	8,	// SPI Enable
+SAEN,	8,	// PWM1 Enable
+SBEN,	8,	// PWM2 Enable
+SCEN,	8,	// UART2 Enable
+SDEN,	8,	// UART2 Enable
+C0EN,	8,	// MMC Enable
+C1EN,	8,	// SDIO Enable
+C2EN,	8,	// SD Card Enable
+LPEN,	8,	// LPE Enable
+
+/* BAR 0 */
+
+S0B0,	32,	// SDMA BAR0
+S1B0,	32,	// I2C1 BAR0
+S2B0,	32,	// I2C2 BAR0
+S3B0,	32,	// I2C3 BAR0
+S4B0,	32,	// I2C4 BAR0
+S5B0,	32,	// I2C5 BAR0
+S6B0,	32,	// I2C6 BAR0
+S7B0,	32,	// I2C7 BAR0
+S8B0,	32,	// SDMA2 BAR0
+S9B0,	32,	// SPI BAR0
+SAB0,	32,	// PWM1 BAR0
+SBB0,	32,	// PWM2 BAR0
+SCB0,	32,	// UART1 BAR0
+SDB0,	32,	// UART2 BAR0
+C0B0,	32,	// MMC BAR0
+C1B0,	32,	// SDIO BAR0
+C2B0,	32,	// SD Card BAR0
+LPB0,	32,	// LPE BAR0
+
+/* BAR 1 */
+
+S0B1,	32,	// SDMA BAR1
+S1B1,	32,	// I2C1 BAR1
+S2B1,	32,	// I2C2 BAR1
+S3B1,	32,	// I2C3 BAR1
+S4B1,	32,	// I2C4 BAR1
+S5B1,	32,	// I2C5 BAR1
+S6B1,	32,	// I2C6 BAR1
+S7B1,	32,	// I2C7 BAR1
+S8B1,	32,	// SDMA2 BAR1
+S9B1,	32,	// SPI BAR1
+SAB1,	32,	// PWM1 BAR1
+SBB1,	32,	// PWM2 BAR1
+SCB1,	32,	// UART1 BAR1
+SDB1,	32,	// UART2 BAR1
+C0B1,	32,	// MMC BAR1
+C1B1,	32,	// SDIO BAR1
+C2B1,	32,	// SD Card BAR1
+LPB1,	32,	// LPE BAR1
+
+/* Extra */
+
+LPFW,	32,	// LPE BAR2 Firmware
diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl
new file mode 100644
index 0000000000..7c7f62fb57
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/charger.asl
@@ -0,0 +1,59 @@
+Device (TCHG)
+{
+	Name (_HID, "INT3403")
+	Name (_UID, 0)
+	Name (PTYP, 0x0B)
+	Name (_STR, Unicode("Battery Charger"))
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/* Return charger performance states defined by mainboard */
+	Method (PPSS)
+	{
+		Return (\_SB.CHPS)
+	}
+
+	/* Return maximum charger current limit */
+	Method (PPPC)
+	{
+		/* Convert size of PPSS table to index */
+		Store (SizeOf (\_SB.CHPS), Local0)
+		Decrement (Local0)
+
+		/* Check if charging is disabled (AC removed) */
+		If (LEqual (\PWRS, Zero)) {
+			/* Return last power state */
+			Return (Local0)
+		} Else {
+			/* Return highest power state */
+			Return (0)
+		}
+
+		Return (0)
+	}
+
+	/* Set charger current limit */
+	Method (SPPC, 1)
+	{
+		/* Retrieve Control (index 4) for specified PPSS level */
+		Store (DeRefOf (Index (DeRefOf (Index
+			(\_SB.CHPS, ToInteger (Arg0))), 4)), Local0)
+
+		/* Pass Control value to EC to limit charging */
+		\_SB.PCI0.LPCB.EC0.CHGS (Local0)
+	}
+
+	/* Initialize charger participant */
+	Method (INIT)
+	{
+		/* Disable charge limit */
+		\_SB.PCI0.LPCB.EC0.CHGD ()
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
new file mode 100644
index 0000000000..58c1c7bea7
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -0,0 +1,144 @@
+External (\_PR.CP00._TSS, MethodObj)
+External (\_PR.CP00._TPC, MethodObj)
+External (\_PR.CP00._PTC, PkgObj)
+External (\_PR.CP00._TSD, PkgObj)
+External (\_PR.CP00._PSS, MethodObj)
+
+Device (TCPU)
+{
+	Name (_HID, EISAID ("INT3401"))
+	Name (_UID, 0)
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/*
+	 * Processor Throttling Controls
+	 */
+
+	Method (_TSS)
+	{
+		If (CondRefOf (\_PR.CP00._TSS)) {
+			Return (\_PR.CP00._TSS)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 0, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+	Method (_TPC)
+	{
+		If (CondRefOf (\_PR.CP00._TPC)) {
+			Return (\_PR.CP00._TPC)
+		} Else {
+			Return (0)
+		}
+	}
+
+	Method (_PTC)
+	{
+		If (CondRefOf (\_PR.CP00._PTC)) {
+			Return (\_PR.CP00._PTC)
+		} Else {
+			Return (Package ()
+			{
+				Buffer () { 0 },
+				Buffer () { 0 }
+			})
+		}
+	}
+
+	Method (_TSD)
+	{
+		If (CondRefOf (\_PR.CP00._TSD)) {
+			Return (\_PR.CP00._TSD)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 5, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+	Method (_TDL)
+	{
+		If (CondRefOf (\_PR.CP00._TSS)) {
+			Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+			Decrement (Local0)
+			Return (Local0)
+		} Else {
+			Return (0)
+		}
+	}
+
+	/*
+	 * Processor Performance Control
+	 */
+
+	Method (_PPC)
+	{
+		Return (0)
+	}
+
+	Method (SPPC, 1)
+	{
+		Store (Arg0, \PPCM)
+
+		/* Notify OS to re-read _PPC limit on each CPU */
+		\PPCN ()
+	}
+
+	Method (_PSS)
+	{
+		If (CondRefOf (\_PR.CP00._PSS)) {
+			Return (\_PR.CP00._PSS)
+		} Else {
+			Return (Package ()
+			{
+				Package () { 0, 0, 0, 0, 0, 0 }
+			})
+		}
+	}
+
+	Method (_PDL)
+	{
+		/* Check for mainboard specific _PDL override */
+		If (CondRefOf (\_SB.MPDL)) {
+			Return (\_SB.MPDL)
+		} ElseIf (CondRefOf (\_PR.CP00._PSS)) {
+			Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+			Decrement (Local0)
+			Return (Local0)
+		} Else {
+			Return (0)
+		}
+	}
+
+	/* Return PPCC table defined by mainboard */
+	Method (PPCC)
+	{
+		Return (\_SB.MPPC)
+	}
+
+#ifdef DPTF_CPU_CRITICAL
+	Method (_CRT)
+	{
+		Return (^^CTOK (DPTF_CPU_CRITICAL))
+	}
+#endif
+
+#ifdef DPTF_CPU_PASSIVE
+	Method (_PSV)
+	{
+		Return (^^CTOK (DPTF_CPU_PASSIVE))
+	}
+#endif
+}
diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl
new file mode 100644
index 0000000000..9ebfb8c9ce
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl
@@ -0,0 +1,78 @@
+Device (DPTF)
+{
+	Name (_HID, EISAID ("INT3400"))
+	Name (_UID, 0)
+
+	Name (IDSP, Package()
+	{
+		/* DPPM Passive Policy 1.0 */
+		ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),
+
+		/* DPPM Critical Policy */
+		ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),
+
+		/* DPPM Cooling Policy */
+		ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),
+	})
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	/* Arg0: Buffer containing UUID
+	 * Arg1: Integer containing Revision ID of buffer format
+	 * Arg2: Integer containing count of entries in Arg3
+	 * Arg3: Buffer containing list of DWORD capabilities
+	 * Return: Buffer containing list of DWORD capabilities
+	 */
+	Method (_OSC, 4, Serialized)
+	{
+		/* Check for Passive Policy UUID */
+		If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {
+			/* Initialize Thermal Devices */
+			^TINI ()
+
+#ifdef DPTF_ENABLE_CHARGER
+			/* Initialize Charger Device */
+			^TCHG.INIT ()
+#endif
+		}
+
+		Return (Arg3)
+	}
+
+	/* Priority based _TRT */
+	Name (TRTR, 1)
+
+	Method (_TRT)
+	{
+		Return (\_SB.DTRT)
+	}
+
+	/* Convert from Degrees C to 1/10 Kelvin for ACPI */
+	Method (CTOK, 1) {
+		/* 10th of Degrees C */
+		Multiply (Arg0, 10, Local0)
+
+		/* Convert to Kelvin */
+		Add (Local0, 2732, Local0)
+
+		Return (Local0)
+	}
+
+	/* Include CPU Participant */
+	#include "cpu.asl"
+
+	/* Include Thermal Participants */
+	#include "thermal.asl"
+
+#ifdef DPTF_ENABLE_CHARGER
+	/* Include Charger Participant */
+	#include "charger.asl"
+#endif
+}
diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl
new file mode 100644
index 0000000000..7113215cd3
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl
@@ -0,0 +1,203 @@
+/* Thermal Threshold Event Handler */
+Method (TEVT, 1, NotSerialized)
+{
+	Store (ToInteger (Arg0), Local0)
+
+#ifdef DPTF_TSR0_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) {
+		Notify (^TSR0, 0x90)
+	}
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) {
+		Notify (^TSR1, 0x90)
+	}
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+	If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) {
+		Notify (^TSR2, 0x90)
+	}
+#endif
+}
+
+/* Thermal device initialization - Disable Aux Trip Points */
+Method (TINI)
+{
+#ifdef DPTF_TSR0_SENSOR_ID
+	^TSR0.PATD ()
+#endif
+#ifdef DPTF_TSR1_SENSOR_ID
+	^TSR1.PATD ()
+#endif
+#ifdef DPTF_TSR2_SENSOR_ID
+	^TSR2.PATD ()
+#endif
+}
+
+#ifdef DPTF_TSR0_SENSOR_ID
+Device (TSR0)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 1)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR0_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (^^CTOK (DPTF_TSR0_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (^^CTOK (DPTF_TSR0_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+}
+#endif
+
+#ifdef DPTF_TSR1_SENSOR_ID
+Device (TSR1)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 2)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR1_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (^^CTOK (DPTF_TSR1_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (^^CTOK (DPTF_TSR1_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+}
+#endif
+
+#ifdef DPTF_TSR2_SENSOR_ID
+Device (TSR2)
+{
+	Name (_HID, EISAID ("INT3403"))
+	Name (_UID, 3)
+	Name (PTYP, 0x03)
+	Name (TMPI, DPTF_TSR2_SENSOR_ID)
+	Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))
+	Name (GTSH, 20) /* 2 degree hysteresis */
+
+	Method (_STA)
+	{
+		If (LEqual (\DPTE, One)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	Method (_TMP, 0, Serialized)
+	{
+		Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))
+	}
+
+	Method (_PSV)
+	{
+		Return (^^CTOK (DPTF_TSR2_PASSIVE))
+	}
+
+	Method (_CRT)
+	{
+		Return (^^CTOK (DPTF_TSR2_CRITICAL))
+	}
+
+	Name (PATC, 2)
+
+	/* Set Aux Trip Point */
+	Method (PAT0, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)
+	}
+
+	/* Set Aux Trip Point */
+	Method (PAT1, 1, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)
+	}
+
+	/* Disable Aux Trip Point */
+	Method (PATD, 0, Serialized)
+	{
+		\_SB.PCI0.LPCB.EC0.PATD (TMPI)
+	}
+}
+#endif
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
new file mode 100644
index 0000000000..a201c03d50
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name(\PICM, 0)		// IOAPIC/8259
+
+/* Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	OSYS,	16,	// 0x00 - Operating System
+	SMIF,	 8,	// 0x02 - SMI function
+	PRM0,	 8,	// 0x03 - SMI function parameter
+	PRM1,	 8,	// 0x04 - SMI function parameter
+	SCIF,	 8,	// 0x05 - SCI function
+	PRM2,	 8,	// 0x06 - SCI function parameter
+	PRM3,	 8,	// 0x07 - SCI function parameter
+	LCKF,	 8,	// 0x08 - Global Lock function for EC
+	PRM4,	 8,	// 0x09 - Lock function parameter
+	PRM5,	 8,	// 0x0a - Lock function parameter
+	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
+	LIDS,	 8,	// 0x0f - LID state (open = 1)
+	PWRS,	 8,	// 0x10 - Power State (AC = 1)
+	PCNT,	 8,	// 0x11 - Processor count
+	TPMP,	 8,	// 0x12 - TPM Present and Enabled
+	TLVL,	 8,	// 0x13 - Throttle Level
+	PPCM,	 8,	// 0x14 - Maximum P-state usable by OS
+	PM1I,	 32,	// 0x15 - System Wake Source - PM1 Index
+
+	/* Device Config */
+	Offset (0x20),
+	S5U0,	 8,	// 0x20 - Enable USB0 in S5
+	S5U1,	 8,	// 0x21 - Enable USB1 in S5
+	S3U0,	 8,	// 0x22 - Enable USB0 in S3
+	S3U1,	 8,	// 0x23 - Enable USB1 in S3
+	TACT,	 8,	// 0x24 - Thermal Active trip point
+	TPSV,	 8,	// 0x25 - Thermal Passive trip point
+	TCRT,	 8,	// 0x26 - Thermal Critical trip point
+	DPTE,	 8,	// 0x27 - Enable DPTF
+
+	/* Base addresses */
+	Offset (0x30),
+	CMEM,	 32,	// 0x30 - CBMEM TOC
+	TOLM,	 32,	// 0x34 - Top of Low Memory
+	CBMC,	 32,	// 0x38 - coreboot mem console pointer
+
+	/* ChromeOS specific */
+	Offset (0x100),
+	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+
+	Offset (0x1000),
+	#include <soc/intel/baytrail/acpi/device_nvs.asl>
+}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+	Store (One, \S3U1)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
+	Store (Zero, \S3U1)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+	Store (One, \S5U0)
+	Store (One, \S5U1)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+	Store (Zero, \S5U0)
+	Store (Zero, \S5U1)
+}
diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl
new file mode 100644
index 0000000000..aa6af717c1
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/gpio.asl
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <soc/iomap.h>
+#include <soc/irq.h>
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 2)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name (_HID, "INT33FC")
+	Name (_CID, "INT33FC")
+	Name (_UID, 3)
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, RMEM)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RMEM._BAS, RBAS)
+		Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		Return (0xF)
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/irq_helper.h b/src/soc/intel/braswell/acpi/irq_helper.h
new file mode 100644
index 0000000000..b19895b583
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/irq_helper.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef ACPI_DEV_APIC_IRQ
+#undef PCI_DEV_PIRQ_ROUTE
+#undef PIRQ_PIC_ROUTES
+#undef PIRQ_PIC
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#endif
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_APIC_IRQ(dev_, 0, a_), \
+	ACPI_DEV_APIC_IRQ(dev_, 1, b_), \
+	ACPI_DEV_APIC_IRQ(dev_, 2, c_), \
+	ACPI_DEV_APIC_IRQ(dev_, 3, d_)
+
+/* Empty PIRQ_PIC definition. */
+#define PIRQ_PIC(pirq_, pic_irq_)
+
+/* Include the mainboard irq route definition. */
+#include "irqroute.h"
diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl
new file mode 100644
index 0000000000..21f1ada02e
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/irqlinks.asl
@@ -0,0 +1,492 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LNKA)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 1)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTA)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTA
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTA, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 2)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTB)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTB
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTB, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 3)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTC)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTC
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTC, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 4)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTD)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTD
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTD, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 5)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTE)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTE
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTE, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 6)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTF)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTF
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTF, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 7)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTG)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTG
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTG, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 8)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTH)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTH
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTH, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl
new file mode 100644
index 0000000000..23987d7d2a
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/irqroute.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include <soc/intel/baytrail/acpi/irq_helper.h>
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include <soc/intel/baytrail/acpi/irq_helper.h>
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
new file mode 100644
index 0000000000..408d2b420f
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel LPC Bus Device  - 0:1f.0
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	#include "irqlinks.asl"
+
+	#include "acpi/ec.asl"
+
+	Device (DMAC)		// DMA Controller
+	{
+		Name(_HID, EISAID("PNP0200"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+		})
+	}
+
+	Device (FWH)		// Firmware Hub
+	{
+		Name (_HID, EISAID("INT0800"))
+		Name (_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	Device (HPET)
+	{
+		Name (_HID, EISAID("PNP0103"))
+		Name (_CID, 0x010CD041)
+
+		Method (_STA, 0)	// Device Status
+		{
+			Return (0xf)	// Enable and show device
+		}
+
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xfed00000, 0x400)
+		})
+	}
+
+	Device(PIC)	// 8259 Interrupt Controller
+	{
+		Name(_HID,EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	Device(LDRC)	// LPC device: Resource consumption
+	{
+		Name (_HID, EISAID("PNP0C02"))
+		Name (_UID, 2)
+
+		Name (RBUF, ResourceTemplate()
+		{
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
+			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
+		})
+
+		Method (_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+
+	Device (RTC)	// Real Time Clock
+	{
+		Name (_HID, EISAID("PNP0B00"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x70, 0x70, 1, 8)
+// Disable as Windows doesn't like it, and systems don't seem to use it.
+//			IRQNoFlags() { 8 }
+		})
+	}
+
+	Device (TIMR)	// Intel 8254 timer
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() {0}
+		})
+	}
+
+	// Include mainboard's superio.asl file.
+	#include "acpi/superio.asl"
+
+#ifdef ENABLE_TPM
+	Device (TPM)		// Trusted Platform Module
+	{
+		Name(_HID, EISAID("IFX0102"))
+		Name(_CID, 0x310cd041)
+		Name(_UID, 1)
+
+		Method(_STA, 0)
+		{
+			If (TPMP) {
+				Return (0xf)
+			}
+			Return (0x0)
+		}
+
+		Name(_CRS, ResourceTemplate() {
+			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
+			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
+			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
+			IRQ (Edge, Activehigh, Exclusive) { 6 }
+		})
+	}
+#endif
+}
diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl
new file mode 100644
index 0000000000..dfa555c834
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/lpe.asl
@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LPEA)
+{
+	Name (_HID, "80860F28")
+	Name (_CID, "80860F28")
+	Name (_UID, 1)
+	Name (_DDN, "Low Power Audio Controller")
+	Name (_PR0, Package () { PLPE })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
+		Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
+		Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_DMA0_IRQ
+		}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_DMA1_IRQ
+		}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_SSP0_IRQ
+		}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_SSP1_IRQ
+		}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_SSP2_IRQ
+		}
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPE_IPC2HOST_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		/* Update BAR0 from NVS */
+		CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)
+		Store (\LPB0, BAS0)
+
+		/* Update BAR1 from NVS */
+		CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)
+		Store (\LPB1, BAS1)
+
+		/* Update LPE FW from NVS */
+		CreateDwordField (^RBUF, ^BAR2._BAS, BAS2)
+		Store (\LPFW, BAS2)
+
+		/* Append any Mainboard defined GPIOs */
+		If (CondRefOf (^GBUF, Local0)) {
+			ConcatenateResTemplate (^RBUF, ^GBUF, Local1)
+			Return (Local1)
+		}
+
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\LPEN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, LPB1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	PowerResource (PLPE, 0, 0)
+	{
+		Method (_STA)
+		{
+			Return (1)
+		}
+
+		Method (_OFF)
+		{
+			Or (PSAT, 0x00000003, PSAT)
+			Or (PSAT, 0x00000000, PSAT)
+		}
+
+		Method (_ON)
+		{
+			And (PSAT, 0xfffffffc, PSAT)
+			Or (PSAT, 0x00000000, PSAT)
+		}
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl
new file mode 100644
index 0000000000..0f8f7465f9
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/lpss.asl
@@ -0,0 +1,712 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (SDM1)
+{
+	Name (_HID, "INTL9C60")
+	Name (_UID, 1)
+	Name (_DDN, "DMA Controller #1")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_DMA1_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S0B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S0EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}
+
+Device (SDM2)
+{
+	Name (_HID, "INTL9C60")
+	Name (_UID, 2)
+	Name (_DDN, "DMA Controller #2")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_DMA2_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S8B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S8EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}
+
+Device (I2C1)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 1)
+	Name (_DDN, "I2C Controller #1")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C1_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S1B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S1EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S1B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C2)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 2)
+	Name (_DDN, "I2C Controller #2")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C2_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S2B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S2EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S2B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C3)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 3)
+	Name (_DDN, "I2C Controller #3")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C3_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S3B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S3EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S3B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C4)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 4)
+	Name (_DDN, "I2C Controller #4")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C4_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S4B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S4EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S4B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C5)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 5)
+	Name (_DDN, "I2C Controller #5")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C5_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S5B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S5EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S5B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C6)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 6)
+	Name (_DDN, "I2C Controller #6")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C6_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S6B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S6EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S6B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (I2C7)
+{
+	Name (_HID, "80860F41")
+	Name (_UID, 7)
+	Name (_DDN, "I2C Controller #7")
+
+	/* Standard Mode: HCNT, LCNT, SDA Hold Time */
+	Name (SSCN, Package () { 0x200, 0x200, 0x6 })
+
+	/* Fast Mode: HCNT, LCNT, SDA Hold Time */
+	Name (FMCN, Package () { 0x55, 0x99, 0x6 })
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_I2C7_IRQ
+		}
+		FixedDMA (0x10, 0x0, Width32Bit, )
+		FixedDMA (0x11, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S7B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S7EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S7B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (SPI1)
+{
+	Name (_HID, "80860F0E")
+	Name (_UID, 1)
+	Name (_DDN, "SPI Controller #2")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_SPI_IRQ
+		}
+		FixedDMA (0x0, 0x0, Width32Bit, )
+		FixedDMA (0x1, 0x1, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\S9B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\S9EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, S9B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (PWM1)
+{
+	Name (_HID, "80860F09")
+	Name (_UID, 1)
+	Name (_DDN, "PWM Controller #1")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\SAB0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\SAEN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}
+
+Device (PWM2)
+{
+	Name (_HID, "80860F09")
+	Name (_UID, 2)
+	Name (_DDN, "PWM Controller #2")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\SBB0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\SBEN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+}
+
+Device (UAR1)
+{
+	Name (_HID, "80860F0A")
+	Name (_UID, 1)
+	Name (_DDN, "HS-UART Controller #1")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_HSUART1_IRQ
+		}
+		FixedDMA (0x2, 0x2, Width32Bit, )
+		FixedDMA (0x3, 0x3, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\SCB0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\SCEN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, SCB1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (UAR2)
+{
+	Name (_HID, "80860F0A")
+	Name (_UID, 2)
+	Name (_DDN, "HS-UART Controller #2")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			LPSS_HSUART2_IRQ
+		}
+		FixedDMA (0x4, 0x4, Width32Bit, )
+		FixedDMA (0x5, 0x5, Width32Bit, )
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\SDB0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\SDEN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, SDB1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl
new file mode 100644
index 0000000000..5ad4e788fc
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/pcie.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001c0000)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		}
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001c0001)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		}
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001c0002)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		}
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001c0003)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		}
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl
new file mode 100644
index 0000000000..e32880ef9b
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/platform.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+Method (_SWS)
+{
+	/* Index into PM1 for device that caused wake */
+	Return (\PM1I)
+}
diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl
new file mode 100644
index 0000000000..7181fb1669
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/scc.asl
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (EMMC)
+{
+	Name (_HID, "80860F14")
+	Name (_CID, "PNP0D40")
+	Name (_UID, 1)
+	Name (_DDN, "eMMC Controller 4.5")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			SCC_EMMC_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\C0B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\C0EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, C0B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Device (EM45)
+	{
+		/* Slot 0, Function 8 */
+		Name (_ADR, 0x8)
+
+		Method (_RMV, 0, NotSerialized)
+		{
+			Return (0)
+		}
+	}
+}
+
+Device (SDIO)
+{
+	Name (_HID, "INT33BB")
+	Name (_CID, "PNP0D40")
+	Name (_UID, 2)
+	Name (_DDN, "SDIO Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			SCC_SDIO_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\C1B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\C1EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, C1B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
+
+Device (SDCD)
+{
+	Name (_HID, "80860F16")
+	Name (_CID, "PNP0D40")
+	Name (_UID, 3)
+	Name (_DDN, "SD Card Controller")
+
+	Name (RBUF, ResourceTemplate()
+	{
+		Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
+		Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
+		{
+			SCC_SD_IRQ
+		}
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^BAR0._BAS, RBAS)
+		Store (\C2B0, RBAS)
+		Return (^RBUF)
+	}
+
+	Method (_STA)
+	{
+		If (LEqual (\C2EN, 1)) {
+			Return (0xF)
+		} Else {
+			Return (0x0)
+		}
+	}
+
+	OperationRegion (KEYS, SystemMemory, C2B1, 0x100)
+	Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
+	{
+		Offset (0x84),
+		PSAT, 32,
+	}
+
+	Method (_PS3)
+	{
+		Or (PSAT, 0x00000003, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+
+	Method (_PS0)
+	{
+		And (PSAT, 0xfffffffc, PSAT)
+		Or (PSAT, 0x00000000, PSAT)
+	}
+}
diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl
new file mode 100644
index 0000000000..8abeb2d91a
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/sleepstates.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
+Name(\_S3, Package(){0x5,0x5,0x0,0x0})
+Name(\_S4, Package(){0x6,0x6,0x0,0x0})
+Name(\_S5, Package(){0x7,0x7,0x0,0x0})
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
new file mode 100644
index 0000000000..9092562275
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <soc/iomap.h>
+#include <soc/irq.h>
+
+Scope(\)
+{
+	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+
+	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
+	Field(IO_T, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x8),
+		TRP0, 8		// IO-Trap at 0x808
+	}
+
+	// Intel Legacy Block
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field (ILBS, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+}
+
+Name(_HID,EISAID("PNP0A08"))	// PCIe
+Name(_CID,EISAID("PNP0A03"))	// PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate()
+	{
+		// Bus Numbers
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+		// IO Region 0
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+		// PCI Config Space
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		// IO Region 1
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+		// VGA memory (0xa0000-0xbffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000,,, ASEG)
+
+		// OPROM reserved (0xc0000-0xc3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000,,, OPR0)
+
+		// OPROM reserved (0xc4000-0xc7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000,,, OPR1)
+
+		// OPROM reserved (0xc8000-0xcbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000,,, OPR2)
+
+		// OPROM reserved (0xcc000-0xcffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000,,, OPR3)
+
+		// OPROM reserved (0xd0000-0xd3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000,,, OPR4)
+
+		// OPROM reserved (0xd4000-0xd7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000,,, OPR5)
+
+		// OPROM reserved (0xd8000-0xdbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000,,, OPR6)
+
+		// OPROM reserved (0xdc000-0xdffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000,,, OPR7)
+
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
+
+		// System BIOS (0xf0000-0xfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000,,, FSEG)
+
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000,,, PMEM)
+
+		// TPM Area (0xfed40000-0xfed44fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				0x00005000,,, TPMR)
+	})
+
+	// Update PCI resource area
+	CreateDwordField(MCRS, PMEM._MIN, PMIN)
+	CreateDwordField(MCRS, PMEM._MAX, PMAX)
+	CreateDwordField(MCRS, PMEM._LEN, PLEN)
+
+	// TOLM is BMBOUND accessible from IOSF so is saved in NVS
+	Store (\TOLM, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
+	Add (Subtract (PMAX, PMIN), 1, PLEN)
+
+	Return (MCRS)
+}
+
+/* Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (PDRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+		Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+		Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+		Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+		Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+		Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+		Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		Return(PDRS)
+	}
+}
+
+Method (_OSC, 4)
+{
+	/* Check for proper GUID */
+	If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	}
+	Else
+	{
+		/* Unrecognized UUID */
+		CreateDWordField (Arg3, 0, CDW1)
+		Or (CDW1, 4, CDW1)
+		Return (Arg3)
+	}
+}
+
+/* IOSF MBI Interface for kernel access */
+Device (IOSF)
+{
+	Name (_HID, "INT33BD")
+	Name (_CID, "INT33BD")
+	Name (_UID, 1)
+
+	Name (RBUF, ResourceTemplate ()
+	{
+		/* MCR / MDR / MCRX */
+		Memory32Fixed (ReadWrite, 0, 12, RBAR)
+	})
+
+	Method (_CRS)
+	{
+		CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
+		Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
+		Return (^RBUF)
+	}
+}
+
+// LPC Bridge 0:1f.0
+#include "lpc.asl"
+
+// USB XHCI 0:14.0
+#include "xhci.asl"
+
+// IRQ routing for each PCI device
+#include "irqroute.asl"
+
+// PCI Express Ports 0:1c.x
+#include "pcie.asl"
+
+Scope (\_SB)
+{
+	// GPIO Devices
+	#include "gpio.asl"
+
+	// LPSS Devices
+	#include "lpss.asl"
+
+	// SCC Devices
+	#include "scc.asl"
+
+	// LPE Device
+	#include "lpe.asl"
+}
diff --git a/src/soc/intel/braswell/acpi/xhci.asl b/src/soc/intel/braswell/acpi/xhci.asl
new file mode 100644
index 0000000000..4d5367acec
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/xhci.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (XHCI)
+{
+	Name (_ADR, 0x00140000)
+	Name (_PRW, Package () { 0x0d, 3 })
+	Name (_S3D, 3) /* Highest D state in S3 state */
+
+	Device (RHUB)
+	{
+		Name (_ADR, 0x00000000)
+		Device (PRT1) { Name (_ADR, 1) }
+		Device (PRT2) { Name (_ADR, 2) }
+		Device (PRT3) { Name (_ADR, 3) }
+		Device (PRT4) { Name (_ADR, 4) }
+	}
+}