Braswell: Add Braswell SOC support

Add the files to support the Braswell SOC.

BRANCH=none
BUG=None
TEST=Build for a Braswell platform

Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 37 insertions, 41 deletions

diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index a985f15b85..25e0bd8dc7 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -23,16 +23,16 @@
 
 Scope(\)
 {
-	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+	/* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */
 
 	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
 	Field(IO_T, ByteAcc, NoLock, Preserve)
 	{
 		Offset(0x8),
-		TRP0, 8		// IO-Trap at 0x808
+		TRP0, 8		/* IO-Trap at 0x808 */
 	}
 
-	// Intel Legacy Block
+	/* Intel Legacy Block */
 	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
 	Field (ILBS, AnyAcc, NoLock, Preserve)
 	{
@@ -48,8 +48,8 @@ Scope(\)
 	}
 }
 
-Name(_HID,EISAID("PNP0A08"))	// PCIe
-Name(_CID,EISAID("PNP0A03"))	// PCI
+Name(_HID,EISAID("PNP0A08"))	/* PCIe */
+Name(_CID,EISAID("PNP0A03"))	/* PCI */
 
 Name(_ADR, 0)
 Name(_BBN, 0)
@@ -58,126 +58,125 @@ Method (_CRS, 0, Serialized)
 {
 	Name (MCRS, ResourceTemplate()
 	{
-		// Bus Numbers
+		/* Bus Numbers */
 		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
 				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
 
-		// IO Region 0
+		/* IO Region 0 */
 		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
 
-		// PCI Config Space
+		/* PCI Config Space */
 		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
 
-		// IO Region 1
+		/* IO Region 1 */
 		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
 
-		// VGA memory (0xa0000-0xbffff)
+		/* VGA memory (0xa0000-0xbffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
 				0x00020000,,, ASEG)
 
-		// OPROM reserved (0xc0000-0xc3fff)
+		/* OPROM reserved (0xc0000-0xc3fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
 				0x00004000,,, OPR0)
 
-		// OPROM reserved (0xc4000-0xc7fff)
+		/* OPROM reserved (0xc4000-0xc7fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
 				0x00004000,,, OPR1)
 
-		// OPROM reserved (0xc8000-0xcbfff)
+		/* OPROM reserved (0xc8000-0xcbfff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
 				0x00004000,,, OPR2)
 
-		// OPROM reserved (0xcc000-0xcffff)
+		/* OPROM reserved (0xcc000-0xcffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
 				0x00004000,,, OPR3)
 
-		// OPROM reserved (0xd0000-0xd3fff)
+		/* OPROM reserved (0xd0000-0xd3fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
 				0x00004000,,, OPR4)
 
-		// OPROM reserved (0xd4000-0xd7fff)
+		/* OPROM reserved (0xd4000-0xd7fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
 				0x00004000,,, OPR5)
 
-		// OPROM reserved (0xd8000-0xdbfff)
+		/* OPROM reserved (0xd8000-0xdbfff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
 				0x00004000,,, OPR6)
 
-		// OPROM reserved (0xdc000-0xdffff)
+		/* OPROM reserved (0xdc000-0xdffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 				0x00004000,,, OPR7)
 
-		// BIOS Extension (0xe0000-0xe3fff)
+		/* BIOS Extension (0xe0000-0xe3fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
 				0x00004000,,, ESG0)
 
-		// BIOS Extension (0xe4000-0xe7fff)
+		/* BIOS Extension (0xe4000-0xe7fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
 				0x00004000,,, ESG1)
 
-		// BIOS Extension (0xe8000-0xebfff)
+		/* BIOS Extension (0xe8000-0xebfff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
 				0x00004000,,, ESG2)
 
-		// BIOS Extension (0xec000-0xeffff)
+		/* BIOS Extension (0xec000-0xeffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
 				0x00004000,,, ESG3)
 
-		// System BIOS (0xf0000-0xfffff)
+		/* System BIOS (0xf0000-0xfffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
-		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
+		/* PCI Memory Region (Top of memory-0xfeafffff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0x00000000, 0x00000000,
-				0x00000000,,, PMEM)
+				0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
+				0x00100000,,, PMEM)
 
-		// TPM Area (0xfed40000-0xfed44fff)
+		/* TPM Area (0xfed40000-0xfed44fff) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
 				0x00005000,,, TPMR)
 	})
 
-	// Update PCI resource area
+	/* Update PCI resource area */
 	CreateDwordField(MCRS, PMEM._MIN, PMIN)
 	CreateDwordField(MCRS, PMEM._MAX, PMAX)
 	CreateDwordField(MCRS, PMEM._LEN, PLEN)
 
-	// TOLM is BMBOUND accessible from IOSF so is saved in NVS
+	/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
 	Store (\TOLM, PMIN)
-	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
@@ -200,7 +199,7 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
 	})
 
-	// Current Resource Settings
+	/* Current Resource Settings */
 	Method (_CRS, 0, Serialized)
 	{
 		Return(PDRS)
@@ -245,29 +244,26 @@ Device (IOSF)
 	}
 }
 
-// LPC Bridge 0:1f.0
+/* LPC Bridge 0:1f.0 */
 #include "lpc.asl"
 
-// USB XHCI 0:14.0
+/* USB XHCI 0:14.0 */
 #include "xhci.asl"
 
-// IRQ routing for each PCI device
+/* IRQ routing for each PCI device */
 #include "irqroute.asl"
 
-// PCI Express Ports 0:1c.x
-#include "pcie.asl"
-
 Scope (\_SB)
 {
-	// GPIO Devices
+	/* GPIO Devices */
 	#include "gpio.asl"
 
-	// LPSS Devices
+	/* LPSS Devices */
 	#include "lpss.asl"
 
-	// SCC Devices
+	/* SCC Devices */
 	#include "scc.asl"
 
-	// LPE Device
+	/* LPE Device */
 	#include "lpe.asl"
 }