diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-04-20 15:20:28 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-25 21:50:48 +0200 |
commit | 32471729d9ebbabe809711ec55568925c6ce2070 (patch) | |
tree | b9f6db4e4969ee5edd6c2571e4f7612121070a9f /src/soc/intel/braswell/acpi/pcie.asl | |
parent | 5fe62efb77a2ecfeecdcc526404712b816e74693 (diff) |
Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi/pcie.asl')
-rw-r--r-- | src/soc/intel/braswell/acpi/pcie.asl | 109 |
1 files changed, 0 insertions, 109 deletions
diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl deleted file mode 100644 index c3f70cc698..0000000000 --- a/src/soc/intel/braswell/acpi/pcie.asl +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* Intel SOC PCIe support */ - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } - } -} |