Braswell: Use Baytrail as Comparison Base

Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 109 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl
new file mode 100644
index 0000000000..5ad4e788fc
--- /dev/null
+++ b/src/soc/intel/braswell/acpi/pcie.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Intel SOC PCIe support */
+
+Device (RP01)
+{
+	Name (_ADR, 0x001c0000)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D)
+			})
+		}
+	}
+}
+
+Device (RP02)
+{
+	Name (_ADR, 0x001c0001)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A)
+			})
+		}
+	}
+}
+
+Device (RP03)
+{
+	Name (_ADR, 0x001c0002)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B)
+			})
+		}
+	}
+}
+
+Device (RP04)
+{
+	Name (_ADR, 0x001c0003)
+
+	Method (_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				#undef PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		} Else {
+			Return (Package() {
+				#define PIC_MODE
+				#include <soc/intel/baytrail/acpi/irq_helper.h>
+				PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C)
+			})
+		}
+	}
+}