diff options
author | Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> | 2015-07-09 00:32:32 -0700 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-07-21 03:15:07 +0200 |
commit | 98d62f20276a79eac1c89988ecaf20ecc0c850f8 (patch) | |
tree | 55187fc840508f942f58d20587c70a2825f05e21 /src/soc/intel/braswell/acpi/dptf/cpu.asl | |
parent | 406effd59075cab212c5bf9c1a12759c8fad50a4 (diff) |
braswell: clean up \_PR entries
All \_PR entries needs to be changed from CPU# to CP##
so that it can support more cores.
BRANCH=none
BUG=chrome-os-partner:38734
TEST=build and boot cyan/strago boards.
Change-Id: I80a79ec8edbce46826140470645b7532ae361f91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ca269a7ffcd2ef16fcef93851e68c2d91104e3e1
Original-Change-Id: I48e73742dc3b11ee6e96f70bcd2d10d01609ad7c
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285700
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10991
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/acpi/dptf/cpu.asl')
-rw-r--r-- | src/soc/intel/braswell/acpi/dptf/cpu.asl | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 9b1930b926..018144c3e1 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,8 +1,8 @@ -External (\_PR.CPU0._TSS, MethodObj) -External (\_PR.CPU0._TPC, MethodObj) -External (\_PR.CPU0._PTC, PkgObj) -External (\_PR.CPU0._TSD, PkgObj) -External (\_PR.CPU0._PSS, MethodObj) +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) External (\_SB.DPTF.CTOK, MethodObj) Device (B0DB) @@ -24,8 +24,8 @@ Device (B0DB) Method (_TSS) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Return (\_PR.CPU0._TSS) + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (B0DB) Method (_TPC) { - If (CondRefOf (\_PR.CPU0._TPC)) { - Return (\_PR.CPU0._TPC) + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (B0DB) Method (_PTC) { - If (CondRefOf (\_PR.CPU0._PTC)) { - Return (\_PR.CPU0._PTC) + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (B0DB) Method (_TSD) { - If (CondRefOf (\_PR.CPU0._TSD)) { - Return (\_PR.CPU0._TSD) + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (B0DB) Method (_TDL) { - If (CondRefOf (\_PR.CPU0._TSS)) { - Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (B0DB) Method (_PSS) { - If (CondRefOf (\_PR.CPU0._PSS)) { - Return (\_PR.CPU0._PSS) + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (B0DB) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { - Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { |