Braswell: Update to end of June.

Remove some CamelCase in acpi.c
Add FSP PcdDvfsEnable configuration parameter.
Add lpc_init and lpc_set_low_power routines.
Remove Braswell reference to make code easier to port to another SOC.

BRANCH=none
BUG=None
TEST=Build and run on cyan

Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10768
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index 540ac84ed8..207f17d579 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -13,6 +13,7 @@ subdirs-y += ../../../cpu/intel/turbo
 
 romstage-y += gpio_support.c
 romstage-y += iosf.c
+romstage-y += lpc_init.c
 romstage-y += memmap.c
 romstage-y += tsc_freq.c
 
@@ -46,6 +47,7 @@ ramstage-y += tsc_freq.c
 # Remove as ramstage gets fleshed out
 ramstage-y += placeholders.c
 
+smm-y += lpc_init.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += spi.c