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authorArthur Heymans <arthur@aheymans.xyz>2019-06-04 14:45:13 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-11-29 09:38:22 +0000
commit56d913eedb2f4f0df0b2210f139d857a829bdf96 (patch)
treee65099a8e855295bda9765823320dc4ec9562ee8 /src/soc/intel/braswell/Makefile.inc
parent2d33c3e6c3ab2427377b9b532b6590aa87340c4e (diff)
soc/intel/braswell: Use sb/intel/common/spi.c
This common implementation is compatible. Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/braswell/Makefile.inc')
-rw-r--r--src/soc/intel/braswell/Makefile.inc4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index cc111da485..d2626e865e 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -20,12 +20,10 @@ romstage-y += iosf.c
romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += smbus.c
-romstage-y += spi.c
romstage-y += tsc_freq.c
postcar-y += memmap.c
postcar-y += iosf.c
-postcar-y += spi.c
postcar-y += tsc_freq.c
ramstage-y += acpi.c
@@ -51,7 +49,6 @@ ramstage-y += scc.c
ramstage-y += sd.c
ramstage-y += smm.c
ramstage-y += southcluster.c
-ramstage-y += spi.c
ramstage-y += tsc_freq.c
ramstage-y += xhci.c
@@ -60,7 +57,6 @@ ramstage-y += placeholders.c
smm-y += lpc_init.c
smm-y += pmutil.c
smm-y += smihandler.c
-smm-y += spi.c
smm-y += tsc_freq.c
verstage-y += pmutil.c