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authorLee Leahy <leroy.p.leahy@intel.com>2015-07-02 11:55:18 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2015-07-06 18:45:23 +0200
commitacb9c0b6616f96357c303964678eac05177a078d (patch)
tree31991144e04b437bb078d8b6a66bc3c081d16da8 /src/soc/intel/braswell/Kconfig
parent2bc9cee0f70f133bb31a79b92ea4d982d55d048d (diff)
Braswell: Update to end of June.
Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
-rw-r--r--src/soc/intel/braswell/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 5b6fa109e1..4f7ed6a7ca 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -27,7 +27,9 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_MODULES
select PARALLEL_MP
select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
+ select PCIEXP_L1_SUB_STATE
select PLATFORM_USES_FSP1_1
select REG_SCRIPT
select SOC_INTEL_COMMON