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authorAaron Durbin <adurbin@chromium.org>2016-08-12 15:00:10 -0500
committerMartin Roth <martinroth@google.com>2016-08-19 03:05:18 +0200
commite8e118dd324e32070a1550e3f8ff90dd6fad72f8 (patch)
treeac4519ee91fd36f1e67d322fe775dc8e4444a785 /src/soc/intel/baytrail
parent3326f1599133fd070d378606d717cc9412fb3aab (diff)
Kconfig: introduce writable boot device notion
Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/baytrail')
-rw-r--r--src/soc/intel/baytrail/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index b79000802e..400978567f 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
select SUPPORT_CPU_UCODE_IN_CBFS