diff options
author | Shelley Chen <shchen@google.com> | 2021-10-20 15:43:45 -0700 |
---|---|---|
committer | Shelley Chen <shchen@google.com> | 2021-11-10 17:24:16 +0000 |
commit | 4e9bb3308e811000eb089be6b03658e4cb9a4717 (patch) | |
tree | dca19104e9f6144736a042203f53de9802b53a7e /src/soc/intel/baytrail | |
parent | 5c163bb86926d982af1ffd93b072ca85070ca1e1 (diff) |
Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail')
-rw-r--r-- | src/soc/intel/baytrail/Kconfig | 4 | ||||
-rw-r--r-- | src/soc/intel/baytrail/acpi/southcluster.asl | 8 | ||||
-rw-r--r-- | src/soc/intel/baytrail/bootblock/bootblock.c | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9f1cb8e820..c2d24b29c6 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -39,10 +39,10 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config MMCONF_BASE_ADDRESS +config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config MMCONF_BUS_NUMBER +config ECAM_MMCONF_BUS_NUMBER int default 256 diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 5f20463c2a..c994fdabbe 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -144,7 +144,7 @@ Name (MCRS, ResourceTemplate() 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, LMEM) - /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + /* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, @@ -184,7 +184,7 @@ Method (_CRS, 0, Serialized) /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) + Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) @@ -198,7 +198,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) @@ -247,7 +247,7 @@ Device (IOSF) Method (_CRS) { CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) - Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS) + Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS) Return (^RBUF) } } diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index fa8283c9f2..3f07a6b439 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -89,7 +89,7 @@ static void setup_mmconfig(void) reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); - reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1; pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; |