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| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2021-05-26 06:40:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-01 05:58:39 +0000 |
| commit | 09133c78dd2c5753802bcf5b7e7eb9b5be9ecf6d (patch) | |
| tree | 72bd269e79922481dc71c7c81606836609a8ffa0 /src/soc/intel/baytrail | |
| parent | cdb81500f1fbfef2865e692e1193e39a56f9bca2 (diff) | |
soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
Add Silicon upd settings for LPSS (GSPI/UART/I2C).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/baytrail')
0 files changed, 0 insertions, 0 deletions