intel/baytrail,broadwell: Move stage cache support function

Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 14 insertions, 33 deletions

diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 3ad6a8f978..d9663462c6 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -13,7 +13,6 @@ romstage-y += iosf.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += spi.c
-romstage-y += stage_cache.c
 romstage-y += tsc_freq.c
 
 postcar-y += iosf.c
@@ -45,7 +44,6 @@ ramstage-y += sd.c
 ramstage-y += smm.c
 ramstage-y += southcluster.c
 ramstage-y += spi.c
-ramstage-y += stage_cache.c
 ramstage-y += tsc_freq.c
 ramstage-y += xhci.c
 ramstage-$(CONFIG_ELOG) += elog.c
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index 211f476712..94e91ca7a1 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -14,6 +14,7 @@
  */
 
 #include <cbmem.h>
+#include <stage_cache.h>
 #include <soc/iosf.h>
 #include <soc/smm.h>
 
@@ -26,3 +27,16 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	char *smm_base;
+	/* 1MiB cache size */
+	const long cache_size = CONFIG_SMM_RESERVED_SIZE;
+
+	/* Ramstage cache lives in TSEG region which is the definition of
+	 * cbmem_top(). */
+	smm_base = cbmem_top();
+	*size = cache_size;
+	*base = &smm_base[smm_region_size() - cache_size];
+}
diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c
deleted file mode 100644
index 4c2a97621a..0000000000
--- a/src/soc/intel/baytrail/stage_cache.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stage_cache.h>
-#include <soc/smm.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
-	char *smm_base;
-	/* 1MiB cache size */
-	const long cache_size = CONFIG_SMM_RESERVED_SIZE;
-
-	/* Ramstage cache lives in TSEG region which is the definition of
-	 * cbmem_top(). */
-	smm_base = cbmem_top();
-	*size = cache_size;
-	*base = &smm_base[smm_region_size() - cache_size];
-}