diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-28 16:26:43 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 09:20:52 +0000 |
| commit | 05498a254d5364efb669f63aa4b042c91c123727 (patch) | |
| tree | 21fe95cd426c1da7a2ea54f44bfcb1566731308d /src/soc/intel/baytrail | |
| parent | e7f4beca19d538c47208b8a1b984cf0e39ff02b4 (diff) | |
src/soc: Get rid of whitespace before tab
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/baytrail')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/gpio.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/msr.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/xhci.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/romstage/early_spi.c | 2 |
4 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 580c4eb80b..93e80cbab2 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -58,8 +58,8 @@ #define GPSSUS_COUNT 44 /* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 #define GPIO_DIR_OUTPUT 0 #define GPIO_DIR_INPUT 1 @@ -317,12 +317,12 @@ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT GPIO_INPUT_NOPU #define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU #define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K #define GPIO_NC GPIO_OUT_HIGH -#define GPIO_DEFAULT GPIO_FUNC0 +#define GPIO_DEFAULT GPIO_FUNC0 /* 16 DirectIRQs per supported bank */ #define GPIO_MAX_DIRQS 16 diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index e735f0116c..689d4d55cc 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -20,10 +20,10 @@ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define SINGLE_PCTL (1 << 11) +#define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 -#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) -#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc diff --git a/src/soc/intel/baytrail/include/soc/xhci.h b/src/soc/intel/baytrail/include/soc/xhci.h index ec643c1725..d509b51a6a 100644 --- a/src/soc/intel/baytrail/include/soc/xhci.h +++ b/src/soc/intel/baytrail/include/soc/xhci.h @@ -33,7 +33,7 @@ # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c index 61e95fabc9..e1e7542ed8 100644 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ b/src/soc/intel/baytrail/romstage/early_spi.c @@ -22,7 +22,7 @@ #include <soc/romstage.h> #include <soc/spi.h> -#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_DELAY 10 /* 10us */ #define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ #define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) |