diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-25 21:07:59 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:09:42 +0200 |
commit | 4a83f1cf24b793db40606febb8e27cee90452590 (patch) | |
tree | 74943b190d2aa7c97da72d59f816157d4bc947e9 /src/soc/intel/baytrail | |
parent | 3c80408fc8aa7b4099493acd7420f8d62ce65a48 (diff) |
src/soc: Add required space before opening parenthesis '('
Change-Id: Ifc47f103492a2cd6c818dfd64be971d34afbe0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16324
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/baytrail')
-rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/romstage/early_spi.c | 2 | ||||
-rw-r--r-- | src/soc/intel/baytrail/sata.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 5c6275d434..b5d18a0aca 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -197,7 +197,7 @@ static void check_device_present(device_t dev) reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } - } else if(!dev->enabled) { + } else if (!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, pci_read_config32(dev, LCTL) | LD); diff --git a/src/soc/intel/baytrail/romstage/early_spi.c b/src/soc/intel/baytrail/romstage/early_spi.c index 5ae3e200f3..61e95fabc9 100644 --- a/src/soc/intel/baytrail/romstage/early_spi.c +++ b/src/soc/intel/baytrail/romstage/early_spi.c @@ -45,7 +45,7 @@ int early_spi_read_wpsr(u8 *sr) SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; /* Wait for error / complete status */ - while(timeout--) { + while (timeout--) { u16 status = SPI16(SSFS); if (status & FLASH_CYCLE_ERROR) { printk(BIOS_ERR, "SPI rdsr failed\n"); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 316ab2ccd7..12484be57c 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -170,7 +170,7 @@ static void sata_enable(device_t dev) reg16 = pci_read_config16(dev, 0x90); reg16 &= ~0x03e0; reg16 |= (config->sata_port_map ^ 0x3) << 8; - if(config->sata_ahci) + if (config->sata_ahci) reg16 |= 0x60; pci_write_config16(dev, 0x90, reg16); |