soc/intel/baytrail/acpi.c: Align with Braswell

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 40 insertions, 46 deletions

diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 8870ef537a..458e2d5121 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -125,18 +125,18 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
-static acpi_tstate_t baytrail_tss_table[] = {
+static acpi_tstate_t soc_tss_table[] = {
 	{ 100, 1000, 0, 0x00, 0 },
-	{ 88, 875, 0, 0x1e, 0 },
-	{ 75, 750, 0, 0x1c, 0 },
-	{ 63, 625, 0, 0x1a, 0 },
-	{ 50, 500, 0, 0x18, 0 },
-	{ 38, 375, 0, 0x16, 0 },
-	{ 25, 250, 0, 0x14, 0 },
-	{ 13, 125, 0, 0x12, 0 },
+	{  88,  875, 0, 0x1e, 0 },
+	{  75,  750, 0, 0x1c, 0 },
+	{  63,  625, 0, 0x1a, 0 },
+	{  50,  500, 0, 0x18, 0 },
+	{  38,  375, 0, 0x16, 0 },
+	{  25,  250, 0, 0x14, 0 },
+	{  13,  125, 0, 0x12, 0 },
 };
 
-static void generate_T_state_entries(int core, int cores_per_package)
+static void generate_t_state_entries(int core, int cores_per_package)
 {
 	/* Indicate SW_ALL coordination for T-states */
 	acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
@@ -148,24 +148,23 @@ static void generate_T_state_entries(int core, int cores_per_package)
 	acpigen_write_TPC("\\TLVL");
 
 	/* Write TSS table for MSR access */
-	acpigen_write_TSS_package(
-		ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table);
+	acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table);
 }
 
 static int calculate_power(int tdp, int p1_ratio, int ratio)
 {
-	u32 m;
-	u32 power;
+	u32 m, power;
 
 	/*
 	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
-	 *
-	 * Power = (ratio / p1_ratio) * m * tdp
 	 */
 
 	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
 	m = (m * m) / 1000;
 
+	/*
+	 * Power = (ratio / p1_ratio) * m * TDP
+	 */
 	power = ((ratio * 100000 / p1_ratio) / 100);
 	power *= (m / 100) * (tdp / 1000);
 	power /= 1000;
@@ -173,7 +172,7 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
 	return (int)power;
 }
 
-static void generate_P_state_entries(int core, int cores_per_package)
+static void generate_p_state_entries(int core, int cores_per_package)
 {
 	int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2;
 	int coord_type, power_max, power_unit, num_entries;
@@ -232,12 +231,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
 
 		/* Add entry for Turbo ratio */
 		acpigen_write_PSS_package(
-			clock_max + 1,		/*MHz*/
-			power_max,		/*mW*/
-			10,			/*lat1*/
-			10,			/*lat2*/
-			control_status,		/*control*/
-			control_status);	/*status*/
+			clock_max + 1,		/* MHz */
+			power_max,		/* mW */
+			10,			/* lat1 */
+			10,			/* lat2 */
+			control_status,		/* control */
+			control_status);	/* status */
 	} else {
 		/* _PSS package count without Turbo */
 		acpigen_write_package(num_entries + 1);
@@ -248,12 +247,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	/* First regular entry is max non-turbo ratio */
 	control_status = (ratio_max << 8) | vid_max;
 	acpigen_write_PSS_package(
-		clock_max,		/*MHz*/
-		power_max,		/*mW*/
-		10,			/*lat1*/
-		10,			/*lat2*/
-		control_status,		/*control */
-		control_status);	/*status*/
+		clock_max,		/* MHz */
+		power_max,		/* mW */
+		10,			/* lat1 */
+		10,			/* lat2 */
+		control_status,		/* control */
+		control_status);	/* status */
 
 	/* Set up ratio and vid ranges for VID calculation */
 	ratio_range_2 = (ratio_turbo - ratio_min) * 2;
@@ -264,8 +263,8 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	     ratio >= ratio_min; ratio -= ratio_step) {
 
 		/* Calculate VID for this ratio */
-		vid = ((ratio - ratio_min) * vid_range_2) /
-			ratio_range_2 + vid_min;
+		vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
+
 		/* Round up if remainder */
 		if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
 			vid++;
@@ -276,12 +275,12 @@ static void generate_P_state_entries(int core, int cores_per_package)
 		control_status = (ratio << 8) | (vid & 0xff);
 
 		acpigen_write_PSS_package(
-			clock,			/*MHz*/
-			power,			/*mW*/
-			10,			/*lat1*/
-			10,			/*lat2*/
-			control_status,		/*control*/
-			control_status);	/*status*/
+			clock,			/* MHz */
+			power,			/* mW */
+			10,			/* lat1 */
+			10,			/* lat2 */
+			control_status,		/* control */
+			control_status);	/* status */
 	}
 
 	/* Fix package length */
@@ -301,20 +300,16 @@ void generate_cpu_entries(const struct device *device)
 		}
 
 		/* Generate processor \_SB.CPUx */
-		acpigen_write_processor(
-			core, pcontrol_blk, plen);
+		acpigen_write_processor(core, pcontrol_blk, plen);
 
 		/* Generate  P-state tables */
-		generate_P_state_entries(
-			core, pattrs->num_cpus);
+		generate_p_state_entries(core, pattrs->num_cpus);
 
 		/* Generate C-state tables */
-		acpigen_write_CST_package(
-			cstate_map, ARRAY_SIZE(cstate_map));
+		acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map));
 
 		/* Generate T-state tables */
-		generate_T_state_entries(
-			core, pattrs->num_cpus);
+		generate_t_state_entries(core, pattrs->num_cpus);
 
 		acpigen_pop_len();
 	}
@@ -343,8 +338,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
 		sci_flags |= MP_IRQ_POLARITY_HIGH;
 
 	irqovr = (void *)current;
-	current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
-	                                        sci_flags);
+	current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags);
 
 	return current;
 }