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| author | Christian Gmeiner <christian.gmeiner@gmail.com> | 2022-10-04 09:35:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-12 13:10:14 +0000 |
| commit | d8fd2deda1e66acd0a6162bbea1d8d1ff524f055 (patch) | |
| tree | bfe5b76816a3e2c542b65c21b5724fdb78b6458d /src/soc/intel/baytrail/xhci.c | |
| parent | 803241c03e4987d5039c2aa4babcf8b3718f559f (diff) | |
soc/intel/ehl: Support maximum memory frequency selection
Makes it possible to configure the maximum allowed/supported DDR memory
frequency on a per mainboard basis.
Test
- Define maximum memory frequency in mainboard devicetree.cb
- Boot into Linux and run 'sudo dmidecode --type 17' to check memory
speed
- Boot into Linux and run 'phoronix-test-suite benchmark ramspeed'
Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/baytrail/xhci.c')
0 files changed, 0 insertions, 0 deletions