diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-21 22:32:00 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-16 20:57:14 +0100 |
| commit | 7837be6cbb9dfacf66d0981e281c3d9a0a35767d (patch) | |
| tree | aff1b53a14f8736a77e2ce29e78b4a07a19c4640 /src/soc/intel/baytrail/tsc_freq.c | |
| parent | 6a360048a1a4f8eaebbf9c4ec75fe4a9543421b2 (diff) | |
baytrail: SMM support
Initialize SMM on all CPUs by relocating the SMM region
and setting SMRR on all the cores. Additionally SMI
is enabled in the south cluster.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
power button turns off board while in firmware.
Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173983
Reviewed-on: http://review.coreboot.org/4892
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc/intel/baytrail/tsc_freq.c')
| -rw-r--r-- | src/soc/intel/baytrail/tsc_freq.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index e4327318da..7795ab45b0 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -21,11 +21,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <baytrail/msr.h> -#if !defined(__PRE_RAM__) -#include <baytrail/ramstage.h> -#else -#include <baytrail/romstage.h> -#endif unsigned long tsc_freq_mhz(void) { @@ -52,6 +47,13 @@ unsigned long tsc_freq_mhz(void) return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } +#if !defined(__SMM__) +#if !defined(__PRE_RAM__) +#include <baytrail/ramstage.h> +#else +#include <baytrail/romstage.h> +#endif + void set_max_freq(void) { msr_t perf_ctl; @@ -74,3 +76,5 @@ void set_max_freq(void) wrmsr(MSR_IA32_PERF_CTL, perf_ctl); } + +#endif /* __SMM__ */ |