baytrail/rambi: S3 support and other updates

baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)

baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)

baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)

baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)

rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)

baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)

rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)

baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)

baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)

rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)

baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)

baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)

rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)

Squashed 13 commits for baytrail/rambi.

Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 41 insertions, 0 deletions

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 49e4c91a13..261c95ae1d 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -20,6 +20,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -29,6 +30,7 @@
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <romstage_handoff.h>
+#include <drivers/uart/uart8250reg.h>
 
 #include <baytrail/iomap.h>
 #include <baytrail/irq.h>
@@ -144,6 +146,42 @@ static void sc_rtc_init(void)
 	rtc_init(rtc_fail);
 }
 
+/*
+ * The UART hardware loses power while in suspend. Because of this the kernel
+ * can hang because it doesn't re-initialize serial ports it is using for
+ * consoles at resume time. The following function configures the UART
+ * if the hardware is enabled though it may not be the correct baud rate
+ * or configuration.  This is definitely a hack, but it helps the kernel
+ * along.
+ */
+static void com1_configure_resume(device_t dev)
+{
+	const uint16_t port = 0x3f8;
+
+	/* Is the UART I/O port eanbled? */
+	if (!(pci_read_config32(dev, UART_CONT) & 1))
+		return;
+
+	/* Disable interrupts */
+	outb(0x0, port + UART8250_IER);
+
+	/* Enable FIFOs */
+	outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR);
+
+	/* assert DTR and RTS so the other end is happy */
+	outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR);
+
+	/* DLAB on */
+	outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR);
+
+	/* Set Baud Rate Divisor. 1 ==> 115200 Baud */
+	outb(1, port + UART8250_DLL);
+	outb(0, port + UART8250_DLM);
+
+	/* Set to 3 for 8N1 */
+	outb(3, port + UART8250_LCR);
+}
+
 static void sc_init(device_t dev)
 {
 	int i;
@@ -176,6 +214,9 @@ static void sc_init(device_t dev)
 		write32(gen_pmcon1,
 			read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 	}
+
+	if (acpi_slp_type == 3)
+		com1_configure_resume(dev);
 }
 
 /*