diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-04 21:45:52 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-05-05 23:38:38 +0200 |
| commit | 3bde3d74c5574d7855d1845130bdd357bd2cb7e4 (patch) | |
| tree | b7f58f0207c6df21c857351673dfd0c1dcaf65af /src/soc/intel/baytrail/southcluster.c | |
| parent | 014baea1ceda67aa5df8bb4fbf20782893915f81 (diff) | |
baytrail: interrupt routing support
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.
There are still a lot of ACPI errors in the kernel with this
change, though.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc/intel/baytrail/southcluster.c')
| -rw-r--r-- | src/soc/intel/baytrail/southcluster.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index f8b4f18472..10c0b896fb 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <baytrail/iomap.h> +#include <baytrail/irq.h> #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> @@ -116,6 +117,23 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +static void sc_init(device_t dev) +{ + int i; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + /* Set up the PIRQ PIC routing based on static config. */ + for (i = 0; i < NUM_PIRQS; i++) { + write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]); + } + /* Set up the per device PIRQ routing base on static config. */ + for (i = 0; i < NUM_IR_DEVS; i++) { + write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); + } +} + /* * Common code for the south cluster devices. */ @@ -412,7 +430,7 @@ static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, - .init = NULL, + .init = sc_init, .enable = southcluster_enable_dev, .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, |