diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:17:51 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 12:47:47 +0000 |
| commit | 26b49cc9a3f027ad6af56e5f6fd572805fe0f30f (patch) | |
| tree | 87c9b0cbf3c0863067534eced5598860edd67c95 /src/soc/intel/baytrail/smm.c | |
| parent | b5320b2dc1a0c2f710929f4a0aa17529b973b62f (diff) | |
soc/intel/baytrail: Align whitespace and comments
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/soc/intel/baytrail/smm.c')
| -rw-r--r-- | src/soc/intel/baytrail/smm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index d16f9189cd..be541da29a 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -76,13 +76,15 @@ static void smm_southbridge_enable(uint16_t pm1_events) printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) pm1_events |= PCIEXPWAK_DIS; + enable_pm1(pm1_events); disable_gpe(PME_B0_EN); /* Set up the GPIO route. */ smm_southcluster_route_gpios(); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) |