baytrail/rambi: S3 support and other updates

baytrail: Change all GPIO related pull resistors from 10K to 20K
Reviewed-on: https://chromium-review.googlesource.com/187570
(cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e)

baytrail: workaround kernel using serial console on resume
Reviewed-on: https://chromium-review.googlesource.com/188011
(cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469)

baytrail: allow dirty cache line evictions for SMRAM to stick
Reviewed-on: https://chromium-review.googlesource.com/188015
(cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca)

baytrail: Optionally pull up TDO and TMS to avoid power loss in S3.
Reviewed-on: https://chromium-review.googlesource.com/188260
(cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6)

rambi: always load option rom
Reviewed-on: https://chromium-review.googlesource.com/188721
(cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9)

baytrail: use new chromeos ram oops API
Reviewed-on: https://chromium-review.googlesource.com/186394
(cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594)

rambi: always show dev/rec screens on eDP connected panel
Reviewed-on: https://chromium-review.googlesource.com/188731
(cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95)

baytrail: stop e820 reserving default SMM region
Reviewed-on: https://chromium-review.googlesource.com/189084
(cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24)

baytrai: update MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/189196
(cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970)

rambi: Put LPE device into ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/189371
(cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413)

baytrail: DPTF: Enable mainboard-specific PPCC
Reviewed-on: https://chromium-review.googlesource.com/189576
(cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612)

baytrail: Add config option for PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189994
(cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5)

rambi: Enable PCIe wake
Reviewed-on: https://chromium-review.googlesource.com/189995
(cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6)

Squashed 13 commits for baytrail/rambi.

Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6957
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 9 insertions, 8 deletions

diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index d4b3d58350..daf759d206 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -31,13 +31,12 @@
 #include <baytrail/pmc.h>
 #include <baytrail/smm.h>
 
-/* Save the gpio route register. The settings are committed from
- * southcluster_smm_enable_smi(). */
-static uint32_t gpio_route;
+/* Save settings which will be committed in SMI functions. */
+static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
 
-void southcluster_smm_save_gpio_route(uint32_t route)
+void southcluster_smm_save_param(int param, uint32_t data)
 {
-	gpio_route = route;
+	smm_save_params[param] = data;
 }
 
 void southcluster_smm_clear_state(void)
@@ -70,7 +69,7 @@ static void southcluster_smm_route_gpios(void)
 	const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
 	const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
 	uint32_t alt_gpio_reg = 0;
-	uint32_t route_reg = gpio_route;
+	uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
 	int i;
 
 	printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
@@ -92,10 +91,12 @@ static void southcluster_smm_route_gpios(void)
 
 void southcluster_smm_enable_smi(void)
 {
+	uint16_t pm1_events = PWRBTN_EN | GBL_EN;
 
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
-	/* Configure events Disable pcie wake. */
-	enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
+	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
+		pm1_events |= PCIEXPWAK_DIS;
+	enable_pm1(pm1_events);
 	disable_gpe(PME_B0_EN);
 
 	/* Set up the GPIO route. */