diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-04 14:32:06 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 19:46:33 +0000 |
| commit | 0b21ad9e8012dba2f4365bfbc3b51e6637eec588 (patch) | |
| tree | 351212996bf76242988a270c53f671fdaa980cf4 /src/soc/intel/baytrail/scc.c | |
| parent | 580bc412c7449a3592e80ac737c3492af6594dfa (diff) | |
intel/cannonlake_rvp: Declare PCIE clock usage
Define PCI express clock usage for cannonlake u and cannonlake y rvp
based on board design.
TEST=Bootable into OS.
Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/baytrail/scc.c')
0 files changed, 0 insertions, 0 deletions